Overview

Best-in-class PCI Express® Verification IP for your IP, SoC, and system-level design testing.

Used by all leading PCIe, IP, and SoC design verification teams for all generations.

The Cadence Verification IP (VIP) for PCI Express® (PCIe®) provides a complete bus functional model (BFM) with thousands of integrated automatic protocol checks for all three protocol layers (TL, DLL, PL) in addition to specific PIPE and PIE. Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.

The VIP for PCIe can be used as a standalone, as a platform for running TripleCheck tests, and\or for enabling SR-IOV, CXL, NVMe or CCIX on top of the base VIP. The VIP for PCIe supports a wide range of verification platforms, all major simulators, and the industry-standard Universal Verification Methodology (UVM). The VIP core is written in native C language for excellent performance, with seamless integration with all verification languages—Universal Verification Methodology (UVM), SystemVerilog, Verilog, and SystemC®.

Supported specification: PCI Express specification versions 7.0 v0.3, 6.1/6.0, 5.0 and corresponding ECNs, Integrity and Data Encryption(IDE) for PCIe 6.0/5.0 and Intel PIPE 6.2.

PCIe diagram

Product Highlights

  • Compliance with PCIe7.0 v0.3 and PCIe 6.1 with support of critical erratas
  • Verifies Root Complex, EndPoint, PHY, and Switch designs for all native widths and downgraded widths
  • Comprehensive protocol checks with 3,300+ built-in checks/assertions
  • Supports both Serial (NRZ, PAM4) and PIPE 6.2 interface (Original Arch, Serdes)
  • Supports Integrity and Data Encryption for PCIe 6.0, PCIe 5.0
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Static and dynamic setting for configuration variables available
  • Packet tracker ad Waveform Debugger present for easy debugging
  • Provides extensive functional coverage, verification plan, and testsuite

Key Features

The following table lists the Important features offered in the Cadence VIP for PCIe:

Feature Name

Description

Device Type
  • Root Complex, End Point, Switch, PHY DUT, Redriver
Interface
  • Serial (NRZ, PAM4) and PIPE 6.2 (Serdes Architecture and Original Architecture)
Link Rate
  • Supports all PCIe speeds: 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32.0GT/s, 64GT/s
Link Width
  • Configurable link width support x1, x2, x4, x8, x12, x16
  • Full support for up and down configuration
PCIe 7.0
  • Serial interface support
  • Doubled clock used in 64.0 GT/s to achieve the new 128.0 GT/s
  • Added new EIEOSQ ordered set encoding
  • Inherited from PCIe 6.0: flit mode and PAM4 encoding
  • Maintain backwards compatibility with all previous generations
  • No equalization flow supported
Equalization
  • No equalization, bypass equalization, and full equalization flows
  • Automatic and user-defined control for preset, cursor values
FLIT support

FLIT support for Gen6 and beyond

  • 1b/1b Flit encoding
  • 8b/10b Flit mode
  • 128b/130b Flit mode
  • FEC and CRC support
Flow Control
  • Flow control scaling
  • Dedicated, Shared, and Merged credit support
  • Optimized UpdateFC
Clock Modes
  • Common Clock Mode, Separate Reference clock with no SSC (SRNS), Separate Reference Clock with Independent SSC (SRIS)

Enumeration
  • Full Enumeration and Bypass Enumeration support

Skew
  • Ability to insert skew between lanes for all generations
  • Reception of packets with skew recognition

Interrupts
  • MSI, MSI-X, INTx

Power Management
  • Full power management support: D-states, ASPM, L1 substates

Link Configurations
  • UpConfiguration and DownConfiguration Support
  • L0 partial (L0p state)
  • Bifurcation modes

Transaction Layer Updates
  • 10-bit, 14-bit tag
  • Orthogonal Header Content (OHC) Support
  • Requester, Destination, and Completer Segment support

System level Features
  • Integrity and Data Encryption (IDE)
  • Data Object Exchange (DOE)
  • Component Measurement and Authentication (CMA)
  • Single Root IO Virtualization (SR-IOV)
  • Address Translation Services (ATS)
  • Process Address Space ID (PASID)
  • Page Request Interface (PRI)
  • Access Control Services (ACS)
  • Deferred Memory Write (DMWr)

Bifurcation
  • Supported by instantiating multiple VIP agents
Clock Jitter
  • Ability to add jitter to clock
Address Space

Support for all types of address spaces:

  • Memory
  • System Memory (Unclaimed by RC/EP BARs)
  • Configuration
  • MSI and MSI-X
SR-IOV
  • EROM
  • Per VF function level reset
  • VF Migration
  • Alternate routine ID (ARI)
  • VF sharing header log files
System plugins
  • System level scoreboard (SVD)
  • System Performance Analyzer (SPA)

Simulation Test Suite

Extensive testsuite, coverage model, and verification plan with clear linkage to the specification for simple and fast compliance testing.

TripleCheck Test Suite

Master Your Tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles

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