Best-in-class UART Verification IP for your IP, SoC and system-level design testing.

Best-in-class UART Verification IP for your IP, SoC and system-level design testing. In production since 2014 on dozens of production designs.

Cadence provides a mature and comprehensive Verification IP (VIP) for the UART protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for UART provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for UART helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog along with the Universal Verification Methodology (UVM).

Supported Specification: Standard UART 16550 Specification

UART diagram

Product Highlights

  • Supports testbench language interfaces for SystemVerilog and UVM.
  • Compliance: Contains predefined checks to verify that the DUT agents adhere to the protocol rules defined in the UART specification
  • Dynamic activation allows to defer the choice of which instances are active until simulation actually begins
  • Extensive callbacks support for TX/RX packets to enable score-boarding and data manipulation
  • Basic SystemVerilog coverage support
  • Packet tracker creation for easy debugging

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Mode

  • Synchronous, Asynchronous

Transmission Mode

  • Full-Duplex, Half-Duplex

Baud Rate

  • Configurable baud rate generation

Word Length

  • Configurable word length (5, 6, 7, or 8-bits)

Stop Bits

  • Configurable stop bits (1, 1.5, or 2-bits)

Error Detection Flags

  • Overrun, Frame, and Parity error

IDLE Frame Insertion/ Detection

  • Supports IDLE frame insertion and detection on transmitter and receiver respectively

TX/RX FIFOs

  • Supports up to 128-bytes FIFO depth for both transmitter and receiver

Auto Flow Control

  • Supports hardware flow control

Extended Features

  • LIN, MODBUS, Driver Enable, IRDA, Smartcard, and LPUART

仿真测试集合

VIP 附带一个场景测试集合,可轻松评估和部署 VIP

如需更多信息请联系我们

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