Best-in-class SPDIF Verification IP for your IP, SoC, and system-level design testing.

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the SPDIF protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SPDIF helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: Indian Standard DIGITAL AUDIO INTERFACE PART 3 CONSUMER APPLICATIONS (IEC 60958-1)

SPDIF diagram

Product Highlights

  • Supports testbench language interfaces for SystemVerilog and UVM
  • Compliance: Contains predefined checks to verify that the DUT agents adhere to the protocol rules defined in the SPDIF specification
  • Dynamic activation allows to defer the choice of which instances are active until simulation actually begins
  • Extensive callbacks support for TX/RX packets to enable score-boarding and data manipulation
  • SV Coverage support
  • Packet tracker creation for easy debugging

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name


Maximum Audio Sample Word Length

  • Supports both 20-bit and 24-bit audio word length format. In 20-bit audio word length format, AUX field will be present

Audio Sample Word Length

  • Supports padding in audio data if audio sample word length is less than the maximum audio word length

Parity Generation

  • Generates parity internally

Preamble Error Injection

  • Transmits erroneous preamble


VIP 附带一个场景测试集合,可轻松评估和部署 VIP




Cadence 在线支持