SMBus Verification IP for your IP, SoC, and system-level design testing.

Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for SMBus provides a complete bus functional model (BFM), integrated automatic protocol checks and coverage model. The VIP for SMBus is designed for easy integration in testbenches at IP, systems-on-chip (SoC), and system levels, and helps to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for SMBus runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: SMBus v3.0

SMBus diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Contains predefined checks to verify that the DUT agents, controller and target, adhere to the supported protocol features
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive SystemVerilog coverage

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

SMBus Devices

  • Controller target, or host

Packet Error Checking

  • Performs PEC on transmit and receive data on applicable packets

Address Resolution Protocol

  • Resolve addresses for devices on the bus

Device Timeout

  • Device timeout condition detection

Bus Protocol

  • All bus protocols with and without a packet error code

Alert Response Address

  • Alert response protocol for device controller capability

Clock Generation and Data Arbitration

  • Clock generation using defined clock timings and data arbitration

Clock Synchronization Between Two Controllers

  • Clock synchronization when more than one controller drives clock

Optional SMBus Signals

  • SMBSUS in suspend-resume mode signal and SMBALERT for (interrupt line for target signal)

仿真测试集合

VIP 附带一个场景测试集合,可轻松评估和部署 VIP

如需更多信息请联系我们

掌握您的工具

教程、文件和当地专家

Cadence 在线支持

通过在线培训、VIP门户、应用笔记和故障排除文章提高您使用Cadence验证IP的效率