JESD204 Verification IP for your IP, SoC, and system-level design testing.

Cadence provides a mature and comprehensive Verification IP (VIP) for the JESD204 protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for JESD204 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for JESD204 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM).

Supported Specification: JESD204B and JESD204C

JESD204 diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Contains predefined checks to verify that the DUT agents, transmitter and receiver, adhere to the supported protocol features
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging of all the transactions on the channels

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Topology

  • Transmitter or receiver configuration

Clock Frequency

  • Any frequency is supported, as the VIP works on the source clock

Initial Lane Alignment

  • Enabling or disabling initial lane alignment

Encoding Type

  • 8b10, 64b66b, and 64b80b encoding modes

64-bit Sync Header

  • Transmission of all types of sync header information, such as, FEC, CRC-3, CRC-12 and command channel

Subclass

  • Subclass0, subclass1, and subclass2

Scrambling

  • Supports scrambling with user-specific initial seed value

Character Replacement

  • Character replacement feature with and without scrambling

Deterministic Delay

  • Deterministic delay for subclass 1 and 2

Transport Layer Parameter

  • Config/register to control transport layer features, such as CS, HD, and F

Lane Control

  • Lane ranging from 1 to 32

Lane to Lane Delay

  • Transmission and reception for cases where lanes are not aligned

Test Mode

  • Layer-wise test mode

Transport Layer Bypass

  • Skip transport layer operation like padding tail bits

仿真测试集合

VIP 附带一个场景测试集合,可轻松评估和部署 VIP

如需更多信息请联系我们

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