I2S Verification IP for your IP, SoC, and system-level design testing.

The Cadence® Verification IP (VIP) for I2S library is a ready-made, highly configurable VIP for the I2S protocol. It allows tests to be run in a pure simulation environment. It provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for I2S is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported Specification: I2S Specification - Philips Semiconductors.

I2S diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Contains predefined checks to verify that the DUT agents, transmitter and receiver, adhere to the supported protocol features
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Dynamic activation to enable setting the VIP as active/passive during run time

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name



  • Fully configurable VIP configuration: Manager/Subordinate, Transmitter/Receiver, Active/Passive

Word Length Programmability

  • Supports 8, 12, 16, 20, 24, 32, and user-defined

Default Transactions

  • Configurable default transactions


  • Full I2S Transmitter and Receiver functionality, DSP Mode, Left Justified, Right Justified, and MultiChannel

Time Division Multiplexing (TDM)

  • Supports 2, 4, 8 Channel Multiplexing with Programmable Word Length

Full Duplex Mode

  • Supports TDM, DSP mode, Left Justified, and Right Justified


VIP 附带一个场景测试集合,可轻松评估和部署 VIP




Cadence 在线支持