Best in class MIPI® M-PHYsm Verification IP for your IP, SoC, and, system-level design testing.

In production since 2011 on dozens of production designs.

Incorporating the latest protocol updates, the mature, highly capable Cadence® Verification IP (VIP) for the MIPI® M-PHYsm Protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. It includes highly configurable and flexible simulation models of all the protocol layers, devices, and transaction types.

Supported Specification: MIPI M-PHY specification v4.0, v4.1, and v5.0.

MIPI M-PHY diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Compliance: Contains predefined checks to verify that the DUT adheres to the protocol rules defined in the M-PHY Specification
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive coverage in SystemVerilog
  • Packet tracker creation for easy debugging

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Specification Compliance

  • Complies with MIPI M-PHY 4.0, 4.1 and 5.0 specification

M-PHY Type 1 and Type 2

  • Supports Type 1 and Type 2

M-PHY Interface

  • Supports serial interface (DpDn) and signaling interface (RMMI)

M-PHY Modes

  • Supports Burst state, ACTIVATED SAVE states (SLEEP and STALL), and hibernate (“HIBERN8”) state

M-PHY Transmission Modes

  • Supports multiple transmission modes with different bit-signaling and clocking schemes
  • Supports multiple transmission speed ranges (PWM G1-G7, HS G1 - HS G5) and rates per BURST mode

Multi-Lane

  • Supports distribution and merging data over one to four lanes, also supports a different number of lanes per
    sub-link (direction)

Test Mode

  • Support for test mode functionality including loop-back mode

CDR

  • Supports Clock Data Recovery

仿真测试集合

VIP 附带一个场景测试集合,可轻松评估和部署 VIP

如需更多信息请联系我们

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