Best-in-class MIPI® DPIsm Verification IP for your IP, SoC and system-level design testing.

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for MIPI® DPIsm Protocols provides a complete bus functional model (BFM), and integrated automatic protocol checks. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for DPI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. DPI VIP is part of DSI VIP. Our VIP for DPI runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: MIPI DPI v2.0

MIPI DPI diagram

Product Highlights

  • generates constrained-random bus traffic
  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • UVM configuration: The user can configure the VIP agent using the UVM config class
  • Key Features

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Transmitter and Receiver

  • Drives or monitors all possible frames

Physical Layer

  • Supports all color coding (16/18/24 bits and configuration 1, 2, 3)

Timing Parameters

  • Supports all frame timing parameters

UVM Configuration

  • The user can configure the VIP agent using the UVM config class

Dynamic Activation Support

  • The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate

仿真测试集合

VIP 附带一个场景测试集合,可轻松评估和部署 VIP

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