Gold standard for CoaXPress device for your IP, SoC, and system-level design verification.

In production since 2018.

This Cadence® Verification IP (VIP) supports the CoaXPress standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for CoaXPress is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

Supported specification: The VIP for CoaXPress supports the specification versions: 1.0, 1.1, and 1.1.1.

CoaXPress diagram

Product Highlights

  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Transaction and memory callbacks for all protocol, model states and device events
  • Transmits snoop transactions by mimicking a dummy interconnect
  • Ability to dynamically change configuration parameters
  • Extensive functional coverage in SystemVerilog
  • Support testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC
  • Compliance Management System verifies protocol, interface, cache coherency

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Configurations

  • Supports up to 16 connections, up to 16 devices

Bit Rates

  • 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps and 6.25Gbps

Encode

  • Supports 8B/10B encoding and decoding for up connections and down connections

Device Discovery

  • Supports Device Discovery process

Pixel Formats

  • Mono, Bayer (all sub types), RGB, RGBA, YUV (all sub types), YcbCr601 (all sub types) and YcbCr709 (all sub types)

Control Data

  • Control commands: memory read, memory write, control channel reset
  • Control ack: final, wait, logical errors, and others
  • Max Control Size

Stream Data

  • Supports stream data packing, Stream markers, Link framing, Single stream, Multi-streams up to 256 streams and Max data size

Bootstrap Registers

  • Supports Bootstrap registers

Triger

  • Supports Trigger and I/O - Trigger acknowledgment 

IDLE

  • Supports IDLE packet

CRC

  • Supports CRC for Steam and Control Data

Transmission Order

  • Supports packet transmission priority 0,1, and 2

Scan Modes

  • Supports Rectangular Image Stream

仿真测试集合

VIP 附带一个场景测试集合,可轻松评估和部署 VIP

如需更多信息请联系我们

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