概述
高速的仿真器，用于 IP 和系统级芯片验证收敛
Cadence Xcelium Logic Simulator 可为 SystemVerilog、VHDL、SystemC®、e、UVM、混合信号、低功耗和X态传播 (X-propagation) 提供业内一流的核心引擎性能。它对特定领域有相应的App，包括混合信号、基于机器学习的测试压缩和功能安全，助力设计团队尽早实现对 IP 和系统级芯片 (SoC) 设计的验证收敛。
核心优势
行业领先的软件仿真
广泛的语言支持
支持 SystemVerilog、VHDL、SystemC、e、UVM 和 IEEE UPF 标准
一流的性能
自动化并行和增量构建技术，支持大型 SoC 设计的编译以及一流的仿真引擎，以实现最佳的回归吞吐量，包括一个多核引擎，用于加快历时较长的测试案例
利用App实现加速
Xcelium App，如混合信号、基于机器学习的测试压缩和功能安全，便于混合和匹配整个设计和验证周期所需的不同技术
App组合
Xcelium App支持与 Xcelium Logic Simulator 协同工作，使设计团队能够为现代 SoC 设计在 IP 和全芯片层面实现最高的验证性能。
机器学习
Xcelium Machine Learning (ML) App 利用专有的机器学习技术来缩短回归时间，可从以往的回归运行中学习并指导 Xcelium 随机引擎，在实现相同覆盖率的前提下大幅度减少仿真周期，或者在特定的覆盖点产生激励捕捉更多的 bug。
混合信号
Xcelium Mixed-Signal App 支持与 Cadence Spectre SPICE 模拟电路仿真器的协同仿真，以及基于先进的 SystemVerilog 实数模型的仿真。
多核
Xcelium Multi-Core (MC) App 可实现 Xcelium 内核级多线程处理，显著缩短长时间运行的高活跃性测试运行时间，例如门级设计测试模式仿真。
安全
Xcelium Safety App 支持串行和并行故障仿真，结合由 Jasper Safety、vManager Safety 和 Midas Safety Planner 组成的 Cadence 安全验证全流程，可高效地执行安全错误注入以符合 ISO 26262 标准要求。
PowerPlayback
Xcelium PowerPlayback (PPB) App 通过 Palladium 硬件仿真器捕获数十亿规模SoC 设计的门级网表波形，进行时序反标后在 Xclium 上进行大规模并行回放，以达到毛刺精确的功耗估计。
X-Pessimism Removal
Xcelium X-Pessimism Removal (XPR) App 采用先进算法，使软件仿真中 “X” 值的传播更加准确，从而缩短调试时间。
客户案例
Xcelium Logic Simulator 客户评价
We use the Xcelium Logic Simulator for our advanced AI/ML and IoT designs, helping accelerate our simulation tasks. We also utilize the Xcelium DMS App to verify our mixed-signal designs. With the Xcelium simulator, we can achieve verification closure and meet our time-to-market goals.
Edward Youssoufian, Vice President of Engineering, Alif Semiconductor
We have extensive experience using the Xcelium Simulator, and the new Xcelium Apps are a useful extension. Our automotive chips must adhere to the ISO 26262 standard, and the Xcelium Safety App has helped us ensure compliance and identify complex bugs using state-of-the-art verification techniques.
Yi Gu, SoC Design Director, AutoChips
The introduction of Xcelium Apps, including the Xcelium PowerPlayback App, allows us to accurately calculate power consumption and tailor the Xcelium Logic Simulator to match our verification demands, ensuring we have the correct functionality and can meet our aggressive time-to-market goals.
Yee-Wei Huang, Vice President and Spokesman, Realtek
By incorporating the Xcelium Machine Learning App as part of our verification flow, we were able to accelerate coverage convergence with fewer regression tests. This helps us meet our aggressive deadlines while maximizing verification performance and overall verification efficiency.
Tatsuya Kamei, Distinguished Engineer, Automotive SoC Business Division, Renesas Electronics
Our team has used Xcelium Logic Simulation to address our verification needs, and the Xcelium Multi-Core App allows us to shorten long-running DFT pattern simulations using multiple cores. Xcelium Apps enable timely validation closure, and we plan to use them in our verification flow.
Roberto Mattiuzzo, Design Manager, Microcontrollers & Digital ICs Group, RF & Communication Division, STMicroelectronics
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