- Significantly reduces time, cost, and risks for low-power design verification
- Requires no knowledge of formal or assertions
- Automatically checks design structure and behavior, power intent, and low-power design guidelines
Enabling exhaustive verification of design functionality with static and dynamic power optimization techniques, the Cadence® JasperGold® Low-Power Verification (LPV) App is the only dedicated formal solution for low-power functional verification. Unlike non-exhaustive simulation-based approaches, the JasperGold LPV App automatically generates assertions that verify that the power description matches the power intent and guidelines specifications in IEEE 1801 standard Unified Power Format (UPF). Then, the app exhaustively verifies that the power modifications did not create any new hazards and are consistent and correct.
Low-power design and optimization techniques can significantly impact the structural and behavioral elements of your original design. These techniques can lead to the need for you to verify the safe entry and exit of all possible low-power modes, in addition to the functional behavior of the design under test (DUT). Because of this, simulation-based verification is often insufficient. An exhaustive formal verification approach is the most effective way to reduce the risk of a fatal bug escape.
With its built-in automation and debug capabilities, the JasperGold LPV App can significantly reduce the design time, cost, and risks from low-power design complexity compared with traditional approaches. Because the app creates a power-aware internal register-transfer level (RTL) model, this model can also be input to other JasperGold Apps for compelling power-aware static and functional verification analyses.
The JasperGold LPV App takes as input the DUT RTL and then uses the corresponding power-intent specifications in UPF to transform the RTL to make it power-aware. With this "new" power-aware internal model, you can:
- Automatically check the design structure and behavior, power intents, and low-power design guidelines
- Verify the interplay between design elements defined in the power description (e.g., isolation and state retention cells) and design elements defined in the RTL description (e.g., clock and control signals) via automatically generated SystemVerilog Assertions
- Export this power-aware RTL model and data to other JasperGold Apps for compelling power-aware static and functional verification analyses
By using the JasperGold LPV App, you can eliminate the need to use traditional approaches such as spreadsheet analysis, automated structural analysis, manual functional analysis, power-aware simulation, and power-related design rule checking (DRC). You won’t need a background in formal or assertions because all property creation and formal analyses are automated by the app. You will work with a familiar waveform display that you can further manipulate with the JasperGold Visualize™ Interactive Debug Environment.