- Combines traditional RTL linting and formal analysis, deriving rich property-based functional checks from the RTL automatically
- Includes comprehensive lint and DFT checks, fully compatible with Xcelium Parallel Simulation
- Helps eliminate common functional design errors ahead of full unit-level or chip-level verification
- Fully integrated with the powerful JasperGold Visualize debug environment, utilizing proven formal intelligence to reduce violation noise, speed debug, and improve waiver handling
Saving many weeks of tedious, error-prone work, the Cadence® JasperGold® Superlint App automatically generates IEEE standard SystemVerilog Assertion (SVA) properties based on your register-transfer level (RTL)—no testbench or stimuli are required. Even if you have no knowledge or experience with SVAs, you’ll be able to generate many valuable properties very quickly. The JasperGold Superlint App also performs a comprehensive range of static lint checks on the RTL code. The lint checks are fully compatible with the Xcelium Parallel Simulator’s HDL Analysis and Linting (HAL) capability.
RTL designers often need to perform basic verification as soon as enough RTL is available, rather than waiting for testbench availability and before handing off the design to verification specialists. Assertion-based verification (ABV) can support an expedited workflow, but writing assertions in standard languages such as SVA or Property Specification Language (PSL) demands specialized knowledge and can be very time-consuming even for experts.
The JasperGold Superlint App can be used early in the design validation process because it automatically extracts structural properties, even from incomplete RTL. These structural properties can then be configured from a wide variety of predefined functional checks such as dead code checks, finite state machine (FSM) checks, and arithmetic overflow checks.
The generated properties can also be ranked, pre-classified, and output in standard SVAs. These formal properties can then be proven using the JasperGold Superlint App, or used in any ABV flow, such as simulation, formal analysis, or emulation, to increase functional coverage and reduce debug time.
Bottom line: the JasperGold Superlint App helps eliminate common functional design errors and makes sure the code is clean before verification starts, improving design quality and shortening the overall schedule.
- Lint and automatic formal checks can be performed by designers with the JasperGold Superlint App, ahead of RTL verification, to eliminate design errors and improve code quality early in the flow
- Generated properties can be used with the JasperGold Formal Property Verification (FPV) App to augment formal verification, and can be exported for use with Xcelium simulation
- Interactive or batch modes are fully supported
- Uses unique Visualize™ technology to let you focus on property grading and disposition of violations, and easy specification of waivers for known or trivial violations. Violation information and waivers are persistent for noise reduction during follow-on runs
"With the ability to find bugs weeks earlier in the design process, we’ve reduced late-stage RTL changes, which enables the team to save additional time when we get to the functional verification stage.”
Hobson Bullman Vice President and General Manager, Technology Services Group, ARM