Formal and Static Verification

Cadence’s formal verification technologies provide an assertion-based methodology to deliver fast, predictable RTL bring-up without test vectors. Formal verification is exhaustive and requires no testbench, saving months of verification effort and increasing design quality by finding more bugs at an earlier stage, compared with other verification methods. Our new Jasper^® technologies provide the broadest range of design-proven apps, along with the unique Visualize™ interactive debug environment, making Cadence’s formal verification more productive and much easier to adopt.