我们全新的动力双剑组合通过两个紧密集成的系统，能够满足当前先进的SoC设计的硅前(pre-silicon)验证需求：包括针对快速可预测的硬件调试而优化的Cadence® Palladium™ Z2企业级硬件仿真系统，以及面向高性能数十亿门软件验证而优化的Cadence Protium™ X2企业级原型验证系统。
Verified with Cadence
了解我们的客户如何利用 Dynamic Duo 来优化验证、确认和 pre-silicon 软件启动之间的工作量分配，以及采用左移方法来加速他们的产品开发过程。
AMD Designs 3rd-Gen EPYC Server Processors for HPC with Dynamic Duo
Palladium and Protium help AMD push emulation in capacity, next-gen testbench design, advanced clocking, and hybrid use.
With twice the useable capacity, 50 percent higher throughput, and faster modular compiler turnaround, we can validate our most sophisticated GPU and SoC designs comprehensively and on schedule.
Narendra Konda, Senior Director, Hardware Engineering, NVIDIA Corporation
The ability to perform design bring-up and transition between the Palladium Z2 emulation and the Protium X2 prototyping platforms in short time provides us with the opportunity to optimize our shift-left deployment for our most challenging SoC designs.
Alex Starr, Corporate Fellow, Methodology Architect, AMD
Best-in-class emulations are key to our success, and Arm uses emulation extensively together with simulation on Arm-based servers to achieve the highest verification throughput.
Tran Nguyen, senior director of Design Services, Arm
The tightly integrated Cadence and Xilinx front-to-back flow allows software developers to use the platform at the earliest possible point during the development flow and to focus on design validation and software development rather than prototype bring-up.
Hanneke Krekels, senior director, Core Vertical Markets, at Xilinx, Inc