Verification has become the biggest challenge in SoC development. However, traditional verification tools haven’t kept pace with how quickly SoC and ASIC design size and complexity are growing. Simulators slow to a grind as RTL and gate design size increase. This, in turn, delays system integration and extends the overall verification cycle.
As the industry's first datacenter-class emulation system, the Palladium® Z1 platform bridges the verification productivity gap to accelerate verification of SoCs, subsystems, and IP blocks, as well as system-level validation.
Compared to the previous generation, the platform, which brings together simulation acceleration and emulation technologies, delivers up to 5X better emulation throughput and, on average, 2.5X better workload efficiency than the closest competitor.
The way that the Palladium Z1 platform manages emulation resources can save you time and effort. The platform’s unique virtual target relocation capability, along with advanced job shaping allocation, avoids recompiles by allowing payloads to be allocated into available resources at runtime. The platform can execute up to 2304 parallel jobs with 4 million gate granularity and scales to 9.2 billion gates.
Compared to the Palladium XP II environment, the new platform offers an up to 44% reduction in power density, along with a reduction in power consumption per emulation cycle by a factor of three or more. The power advantages are a result of:
Its rack-based blade architecture results in a 92% smaller footprint and 8X better gate density, compared to the Palladium XP II platform. The Palladium Z1 processor-based compute engine is also designed with massive parallelism, delivering 4X better user granularity than its nearest competitor.
Through a compile flow, the Palladium Z1 platform is congruent with the Protium S1 FPGA-Based Prototyping Platform and the Protium X1 Enterprise Prototyping Platform for software development, system validation, and hardware regressions.
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Due to the Palladium Z1 platform's capacity to handle our billion gate-class designs and its highly sophisticated debug and advanced multiuser capabilities, all in a small form factor, we will be able to design and deliver our next generation GPU and Tegra designs with high quality and on schedule.
Narenda Konda, Director of Engineering, NVIDIA
The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four-million-gate verification payloads to multi-billion gate designs.
Daniel Diao, Deputy General Manager of the Turing Processor Business Unit, Huawei
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