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Key Benefits
- 企业级可靠性和可扩展性，将仿真吞吐量提高 5 倍
- 借助高级虚拟目标重定位和任务重塑功能，提高资源利用效率
- 使用基于刀片式机架结构，将占地面积减少 92%
- 应用 Palladium Cloud 可实现安全、可扩展以及定制化容量需求
验证已成为系统级芯片 (SoC) 开发流程中的最大挑战。但是，传统的验证工具无法跟上 SoC 和 ASIC 在设计规模和复杂性方面的增长速度。随着 RTL 级和门级设计的尺寸不断增加，传统仿真工具的速度之慢令人抓狂。这会拖延系统集成的进度，并延长整个验证周期。
Palladium® Z1 平台是业内首个数据中心级硬件仿真加速系统，它弥合了验证效率的差距，用于加速 SoC、子系统、IP 级验证以及系统级验证流程。
与上一代产品相比，该平台融合了仿真加速和硬仿技术，与实力相当的竞争对手相比，其仿真吞吐量高出 5 倍，工作负载效率平均高出 2.5 倍。
Palladium Z1
该平台易于管理和扩展，可实现以下几点：
- 可编译基于不同工作负载的数据库，单个工作站上每小时的编译性能高达 140MG
- 分配尽可能多的工作负载
- 根据优先级运行工作负载
- pre-silicon 和post-silicon的错误调试
智能资源分配
Palladium Z1 平台管理资源的方式可以节省您的时间和精力。该平台提供独特的虚拟目标重定位功能以及高级任务塑造分配功能，允许在运行时将有效负载分配至可用资源，从而避免重新编译。平台最多可以执行 2304 个并行任务，具有 400 万门级最小任务粒度，并可以扩展到 92 亿门。
与 Palladium XP II 环境相比，Z1平台可将功耗密度降低多达 44％，并且每个硬仿周期的功耗可降低三倍或以上。这种功耗优势源自以下几点：
- 系统利用率和并行用户数量平均提高 2.5 倍
- 超过5倍的吞吐量
- 每小时高达 140MG 的编译效率
- 出色的调试深度和上传速度
与 Palladium XP II 平台相比，Z1平台采用基于刀片式机框架构，可减少 92% 的面积占用，并将门密度提高 8 倍。基于 Palladium Z1 处理器的计算引擎还具有大规模并行功能，与实力相当的竞争对手相比，提供4倍更小的用户粒度。
在编译流程上，Palladium Z1 平台兼容与基于 Protium S1 FPGA 的原型开发平台和 Protium X1 企业级原型验证开发平台，可用于软件开发、系统验证和硬件回归。
主要功能
- 基于处理器架构的计算引擎和 Verification Xccelerator Emulator (VXE) 软件可将编译速度提高 2 倍，更高的性能验证，并灵活的支持新的使用模式
- Virtual Verification Machine (VVM) 支持交互式离线调试
- Cadence Xcelium® 仿真器支持hot-swap从软仿真切换到硬仿加速，无需重新编译
- 通过快速、自动、智能的编译器实现快速环境搭建
- 借助全面的 Cadence SpeedBridge® Adapter 产品组合和 Accelerated Verification IP，实现快速的系统级环境搭建
- 借助 Cadence Joules™ RTL Power Solution ，可实现动态功耗分析和验证
- 支持针对USB 和 PCI Express®的预认证和配置的 Emulation Development Kit (EDK) 产品组合，实现快速驱动程序开发和设计验证
- 支持覆盖率和metric-driven的验证
- 提供hybrid环境，可对设计和嵌入式仿真平台进行早期的硬件/软件验证，以实现全面的验证和重用方法
- 通过 Cadence Stratus™ High-Level Synthesis (HLS) 提供高级别综合，使您可以将高级别抽象模型集成到系统验证环境
- 通过面向 SoC 的 Cadence Perspec™ System Verifier 支持基于案例的验证，从而减少复杂的由覆盖范围驱动的系统级测试开发时间
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相关产品
- Cadence Verification Suite
- Palladium Hybrid
- Palladium Dynamic Power Analysis
- Protium S1 Desktop Prototyping Platform
- [REDIRECT] Protium X1 Enterprise Prototyping Platform
- SpeedBridge Adapters
- Xcelium Logic Simulation
- VirtualBridge Adapters
- Emulation Development Kit
- Accelerated Verification IP
- QuickCycles Service
- Palladium Cloud
- Virtual Debug Interface for Software Debuggers
Resource Library
Video (35)
- Dynamic Duo (short version) in 16x9
- AMD Designs 3rd-Gen EPYC Server Processors for HPC with Dynamic Duo
- Pushbutton migration from emulation to prototyping based on Protium platform
- Conquer IP Functional Verification with Formal and Simulation Approach
- +Perspec on Palladium - New Efficient Bus-Performance Verification Techniques
- Productive Design: Hardware/Software Co-Verification with Virtual Debugging from Simulation to Prototyping
- Do’s and Don’ts of Emulating Next-Generation Multi-Billion-Gate Ethernet and InfiniBand Interconnect Devices While Optimizing Verification Productivity and Meeting Development Schedu
- GSP Emulation with Palladium Platform and Prototyping with Protium Platform
- SoC Firmware Debugging Tracer in Emulation Platform
- Improving Firmware Validation Productivity and Debug Efficiency Using Palladium Z1 Platform and Indago Debug Analyzer
- Digital Twin Case Study: Applying Emulation-Based Verification of SoC Using Tactical Software
- Create Palladium Design Equivalent to Both Specification and Gate Implementation on Silicon
- 400G以太在Palladium加速器上的仿真加速实践
- DFT DFD verification acceleration on Palladium
- Accelerate Baidu Kunlun AI chip development based on Palladium Z1 platform
- Accelerating software bring up and debug on emulator with a fluent migration from Palladium to Protium
- Fujitsu Designing the World’s Leading Innovations with Cadence Intelligent System Design
- Mom, I Have a Digital Twin? Now You Tell Me?
- Marvell Gains High Confidence for Silicon Tapeout Using Palladium Emulator to Validate Processor
- Early Firmware Development on Palladium and Protium, Enables 1st Silicon Success at Toshiba Memory
- Green Hills Software Partners with Cadence to Accelerate Embedded System Safety and Security
- Building better aerospace and defense electronics: emulate before you fabricate
- Cadence Delivers Verification Throughput
- Palladium and Protium Dynamic Duo
- Accelerate Your Time to Debug Root Cause
- NVIDIA Partners with Cadence to Overcome Chip Design Challenges
- The Palladium Solution and SoC Emulation for 16nm Automotive Devices at NXP
- Using the Cadence VirtualBridge Emulator with the Palladium Platform
- Taking FPGA-Based Prototyping to the Next Level
- CDNLive India – A Closer Look at State-of-the-Art Verification Techniques and Methodologies
- Palladium Z1: Advanced Job Re-shaping
- Emulating Nvidia GPUs
- NVIDIA Handles Complexity with Palladium Z1 Platform
- Verify Smarter with Industry's First Datacenter-Class Emulation System
- National and Cadence Building a More Efficient Chip Design Flow
Datasheet (11)
- Memory Model Portfolio for Palladium Series Datasheet
- VirtualBridge Adapter for PCI Express 2.0/3.0 Datasheet
- Virtual JTAG Virtual JTAG Debug Interface Datasheet
- Palladium Z1 Enterprise Emulation Platform Datasheet
- Cadence SpeedBridge Adapter for USB 2.0 Host Datasheet
- Cadence SpeedBridge Adapter for PCI Express 3.0 Datasheet
- Cadence SpeedBridge Adapter for Serial ATA (SATA) Datasheet
- SpeedBridge Adapter for USB 3.0 Devices Datasheet
- Cadence SpeedBridge Adapter for Ethernet Datasheet
- Cadence SpeedBridge Adapter for Serial-Attached SCSI (SAS) Datasheet
Press Releases (20)
- Cadence联手Arm，合作加速超大规模计算和5G通信SoC开发
- Nuvoton Accelerates the Development of its MCU Designs with the Cadence Palladium Z1 Enterprise Emulation Platform
- Cadence to Optimize Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development
- Acacia Communications Adopts Cadence Palladium Z1 Enterprise Emulation Platform to Accelerate Optical Networking Development
- Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing
- Cadence Palladium Z1 Enterprise Emulation Platform Enables GUC to Accelerate SoC Design
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Cadence Ushers in New Era of Datacenter-class Emulation with Palladium Z1 Enterprise Emulation Platform
- Altair Semiconductor Adopts Cadence Palladium XP Platform for Advanced IoT SoC Development
- Realtek Accelerates System-on-Chip Verification with Cadence Palladium XP Platform
- Cadence Announces Next-Generation JasperGold Formal Verification Platform
- Media Alert: Cadence to Showcase System Design and Verification Solutions at DVCon US 2015
- M31 Technology Adopts Cadence Verification IP to Achieve 2.5X Faster Verification
- DMP Adopts Cadence Palladium XP Platform to Accelerate High Performance Graphic IP Core Development
- Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification
- Cadence Introduces Automotive Functional Safety Verification Solution, Reducing ISO 26262 Compliance Preparation Effort by up to 50 Percent
- CSR Selects Cadence Palladium XP Platform for Development of ARM-based Automotive Infotainment Systems
- HiSilicon Expands Cadence Palladium XP Platform Usage For Mobile and Digital Media SoC and ASIC Development
- Cadence Redefines Verification Planning and Management with Incisive vManager Solution
- Ricoh Selects Cadence Palladium XP Platform for Next-Generation Multifunction Printer SoC Development
Customer Presentation (8)
- Pushbutton migration from emulation to prototyping based on Protium platform
- Conquer IP Functional Verification with Formal and Simulation Approach
- +Perspec on Palladium - New Efficient Bus-Performance Verification Techniques
- Productive Design: Hardware/Software Co-Verification with Virtual Debugging from Simulation to Prototyping
- SoC Firmware Debugging Tracer in Emulation Platform
- Digital Twin Case Study: Applying Emulation-Based Verification of SoC Using Tactical Software
- 400G以太在Palladium加速器上的仿真加速实践
- Accelerate Baidu Kunlun AI chip development based on Palladium Z1 platform
Customers
Due to the Palladium Z1 platform's capacity to handle our billion gate-class designs and its highly sophisticated debug and advanced multiuser capabilities, all in a small form factor, we will be able to design and deliver our next generation GPU and Tegra designs with high quality and on schedule.
Narenda Konda, Director of Engineering, NVIDIA
The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four-million-gate verification payloads to multi-billion gate designs.
Daniel Diao, Deputy General Manager of the Turing Processor Business Unit, Huawei
Training
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview
