Learn how this Dynamic Duo provide performance at 10s of MHz for billion gate sized designs, in a unified compile and debug environment for fast bring-up and full hardware/software debugging
To undertake comprehensive system-level SoC/ASIC verification, you need to stress and validate your design in a scalable verification environment—one that offers a high degree of control and visibility, applies system-level stimulus to the design, and verifies the performance and behavior of the integrated system. Using Cadence® high-throughput emulation technology, design and verification teams can rapidly bring-up, verify, debug, and turn around their hardware and software designs using realistic system-level environments.
Our simulation acceleration technology allows you to extend and reuse your existing simulation verification environment and accelerate it far beyond software simulator speed at both RTL and gate levels. It also offers both signal-based acceleration (SBA) and advanced transaction-based acceleration (TBA) methodologies to further increase performance. SBA allows users to accelerate the existing software simulator verification environment without changes to the existing methodology or testbench environment. TBA enables the simulation environment to run up to full emulation speed while maintaining the flexibility and testbench reuse of the simulation environment. The Cadence accelerated verification intellectual property (VIP) library provides off-the-shelf transactors for the most common protocols.
What’s more, when you tap into the integrated tool suite, you’ll be able to achieve much more powerful results:
Compiles databases for different workloads, with up to 140MG per hour compile times on a single workstation
