Overview

Redefining Signal and Power Integrity Analysis with Sigrity X

Step into the future with Sigrity X Platform – where innovation meets optimization. Unlock the key to flawless signal and power integrity in your PCB and IC package designs, and leap far beyond the current limits of signal integrity (SI)/power integrity (PI) technology. Imagine effortlessly navigating the complexities of electronic design, and not just meeting, but shattering your time-to-market targets with precision and ease.

With Sigrity X, you're not just working with another tool; you're unlocking seamless in-design analysis synergy within the Allegro X PCB and IC Package platforms. Dive into a comprehensive suite of SI/PI analysis, in-design interconnect modeling, and PDN analysis tools designed to supercharge your performance, ensuring your projects not only meet but exceed deadlines and budgets.

Harness the power of the Sigrity X Platform for flawless performance and reliability success in your next design.

Sigrity X 平台

端到端 SI/PI 分析平台，用于 PCB 和 IC 封装设计

Sigrity X Aurora Sigrity X IBIS 建模 Sigrity X PowerSI Sigrity X Starter Kit Sigrity X XtractIM Sigrity X SystemPI Sigrity X Advanced SI Sigrity X OptimizePI Sigrity X SPEEDEM Sigrity X 拓扑结构 Explorer
Sigrity X Aurora Sigrity X IBIS 建模 Sigrity X PowerSI Sigrity X Starter Kit Sigrity X XtractIM Sigrity X SystemPI Sigrity X Advanced SI Sigrity X OptimizePI Sigrity X SPEEDEM Sigrity X 拓扑结构 Explorer

Key Benefits

Deliver 10X Design Productivity to Meet Your Time-to-Market Goals

Unmatched Performance

Experience up to a 10X performance increase, enabling you to meet your time-to-market requirements effectively

Enhanced Accuracy

Sigrity X Platform's advanced algorithm delivers precise SI/PI analysis, enabling 3x more iterations on PCB or IC designs while meeting schedules

In-Design Analysis

Easily navigate through complex simulations by seamlessly integrating with Allegro X Design and Allegro X Advanced Package Designer Platforms

Applications

Tackle SI and PI Analysis Challenges for PCB and IC Package Design

  • Signal and Power Integrity Analysis for IC Package Design

    Experience superior electrical performance analysis for IC packaging with Sigrity X Platform. Seamlessly integrated with Allegro X Advanced Package Designer Platform, it offers traditional SI/PI analysis for pre-layout, in-design, and post-layout stages. Analyze early in the design cycle using "what if" scenarios to set accurate design constraints and reduce iterations. By reading and writing directly to Allegro X, it ensures fast, accurate integration of design and analysis results. Featuring a SPICE-based simulator and patented hybrid field solvers for 2D and 3D structure extraction, supporting power-aware IBIS models and transistor-level models when necessary.

     

    Explore high-speed signals pre-layout to compare alternatives or post-layout for comprehensive analysis. The design setup workflow includes full-package reflection and crosstalk simulations, interconnect extraction, material details, and differential pair management. Streamline your process with full-wave 3D interconnect model extraction, distributed computing support, automatic port definitions, and detailed 3D geometry views, ensuring precise impedance, coupling, reflection, crosstalk, and IR drop analysis.

    Signal and Power Integrity Analysis for IC Package Design
Signal and Power Integrity Analysis for PCB Design
Signal and Power Integrity Analysis for IC Package Design

Next Steps

Ready to Get Started with Sigrity X Platform?

Customer stories

Discover Inspiring Success Stories Enabled by the Sigrity X Platform

GLOBALFOUNDRIES Accelerates Turnaround Time by 12X Using Sigrity X
IAC and Cadence
Corning Provides Reliable Optical Solution to the World Using Sigrity X

endorsements

See What Customers Have to Say

Capabilities

Design with Confidence and Increase Performance

分布式仿真

Sigrity X 的分布式仿真可极大地提高内核利用率，利用多台计算机对整个信号组进行仿真，时间范围与传统的最坏情况分析相同，从而改变您的整个设计周期。这一创新功能可确保进行全面分析，有效发现串扰或同步开关噪声等关键问题，增强对原型设计的信心。Sigrity X 的仿真速度提高了 10 倍，有助于缩短设计周期，提高项目质量，使您能够高效满足紧迫的工期要求。

利用设计同步的信号和电源完整性优化设计流程

Sigrity X 平台和 Allegro X 平台环境的紧密集成，可以充分发挥设计同步分析的优势，在 PCB 和 IC 设计的早期阶段及时发现并纠正设计问题。这种无缝集成大有裨益：工程师可直接在设计工具中使用业界领先的仿真引擎，实时发现并修复信号和电源问题。您可以通过高效、高质量的设计，减少成本高昂的返工，按时完成任务，确保成本不超出预算。

增强信号完整性

Sigrity X 平台提供基于 SPICE 的仿真器和混合场求解器，用于提取 2D/3D 结构，支持兼顾电源影响的 IBIS 模型和晶体管级模型。通过回流路径工作流程确保电流拥有高效的回流路径，并可直接在 Allegro X 平台内进行全面的布线前和布线后高速信号分析。Sigrity X 直接集成到用于电磁分析的 Clarity 3D Solver 之中，可及早发现信号和电源问题，最大限度地减少迭代次数，加快产品上市，确保您可以在预算范围内按时交付产品。

全面的电源完整性

Sigrity X Comprehensive Power Integrity
Sigrity X 平台提供完整的工具套件，用于进行各种系统级分析，如电源域分析、DC 电源完整性分析、压降分析和电源纹波分析。使工程师能够在不牺牲准确度的前提下，快速应对 SI/PI 中的多重挑战。

先进的互连模型提取

Sigrity X 使您能够创建精确的 RLC、IBIS 或 SPICE 集成电路封装电气模型，其速度比使用混合电磁 (EM) 求解器的其他方法快 10 倍。这些模型支持全面的系统级信号和电源完整性仿真，包括驱动器、接收器和互连器件，并提供针对宽带优化性能的选项。Sigrity X 还提供 IBIS 或 SPICE 电路网表格式的简约寄生模型，具有堆叠检查、C4 bump 和焊球创建以及信号和电源/接地网选择等易于使用的工作流程，确保了精确高效的封装性能验证。

Products

Accurate and Efficient SI/PI Analysis Helps Meets Compressed Schedules of High-Speed Electronic Products

Sigrity X Aurora

Sigrity X Aurora, integrated with all Allegro X Platforms, empowers designers to swiftly detect and correct signal and power integrity issues early, eliminating the need for expert inspections and ensuring projects stay on schedule and within budget. This seamless in-design analysis methodology supports comprehensive signal and power integrity analysis at every design stage, enabling precise "what if" scenario planning to set accurate constraints and minimize iterations.

  • Measure any voltage drop between the source and the sink and visualize the results on the design canvas as voltage, voltage drop, or current density
  • Deliver products on time and within budget with a 10X performance increase while maintaining the trusted accuracy for which Sigrity X tools are known
  • Provides access to Sigrity X Aurora PCB analysis from the design engineer and layout designer’s desktop, making analysis results actionable with real-time design edits
  • Set up a design in Allegro X Advanced Package Designer for full-package reflection and crosstalk simulations, as well as interconnect extraction, materials and cross-section details, DC (power) net identification, default and specific simulation models, and differential pair management
  • Streamlines full-wave 3D interconnect model extraction with support for distributed computing, fully automatic port definitions and de-embedding, and the ability to view 3D geometry and S-parameters
  • Analysis Screenings: Impedance, coupling, reflection, crosstalk, IR drop, and more

Sigrity X Advanced SI

Sigrity X Advanced SI technology offers leading-edge signal integrity analysis for PCB and IC packaging designs, covering DC to over 56GHz with advanced features like automated die-to-die SI analysis, topology exploration, and simulation for high-speed interfaces. Supporting IBIS-AMI models and customizable compliance kits, it ensures your designs meet rigorous standards while leveraging frequency domain, time domain, and statistical analysis methods.

  • Accurate handling of non-ideal power delivery system influences on SI
  • Concurrently evaluate SI effects such as losses, reflections, crosstalk, and simultaneous switching output (SSO)
  • Support for industry-standard IBIS-AMI transmitter and receiver models enables simulations of channel behavior for serial links with chips from multiple suppliers
  • Highly automated measurement and reporting capabilities

Sigrity X IBIS Modeling

Sigrity X IBIS Modeling enables accurate simulations for high-speed interfaces with power-aware IBIS models, million-bit channel simulations, and IBIS-AMI model creation, ensuring detailed and efficient simulations for complex topologies. Integrated with Sigrity X Advanced SI and Sigrity X Aurora technologies, it supports seamless modeling and analysis of serial links and parallel bus topologies, maintaining transistor-level accuracy and compliance with IBIS 7.0 specifications.

  • Verifies behavioral model accuracy versus the original transistor model with an included time domain simulation wizard
  • Accuracy checks are included as part of the model conversion process
  • Highly automated and easy to use for those familiar with available IBIS model formats
  • All IBIS BIRD95/BIRD98 power-aware effects are included
  • Wizard-based approach guides the user through the creation of an IBIS-AMI model
  • IBIS-AMI models are automatically compiled and created for Windows and Linux implementations
  • General topology environment for creating signal testbenches
  • Parallel bus simulation environment where dozens of signals can be simulated switching simultaneously along with the PDN and voltage regulator module (VRM) 

Sigrity X OptimizePI

The highly flexible topology environment empowers you to conduct comprehensive power integrity analysis from the voltage source to all connected components, enabling early "what-if" scenarios to optimize performance specifications across multi-fabric power delivery networks (PDN). As design progresses, extracted PDN models can be seamlessly integrated to reflect detailed structures, and in case of design failure during signoff, the adaptable topology interface helps pinpoint issues by allowing ideal PDN models to be swapped in and out with ease.

  • Eliminates decap over-design for PCBs and IC packages
  • Reduces PDN cost for new designs and post-production products
  • Develops effective decap guidelines for packaged components
  • Optimizes a PDN across the PCB and IC package interface
  • Robust and proven underlying hybrid EM/circuit analysis technology
  • Intuitive and interactive visualization of PDN performance
  • Simple to set up for pre- and post-layout decap optimization
  • Visualize the power portion of your schematics with Allegro X, as well as in Mentor, Zuken, and Altium flows.
  • Unique device impedance and EMI resonance checking

Sigrity X PowerSI

Sigrity X PowerSI technology offers fast, accurate electrical analysis for full IC packages or PCBs, enabling comprehensive studies on signal and power integrity, EMI, and frequency domain simulations. Cloud-ready and compatible with various layout databases, Sigrity X PowerSI helps develop pre-layout guidelines and post-layout performance verification without the need for prototypes.

  • Facilitates AC analysis to assess voltage distribution across ground planes
  • Establishes power delivery network (PDN) guidelines for IC packages and boards
  • Evaluates electromagnetic coupling between geometries to enable better component, via, and decap placement
  • Extracts frequency-dependent S, Z, and Y parameters for package and board modeling for subsequent time domain SSN simulation
  • Anticipates energy leaks with near-field ration display
  • Assesses decoupling capacitor strategies and verifies placement effects Enables broadband modeling including accurate DC performance characterization
  • Integrates seamlessly with 3D solutions for IC packages and boards
  • Distributed computing option accelerates analysis time (additional license required)
  • Strong HSPICE flow support
  • Optimized for flows with Allegro X Design Platform, Allegro X Advanced Package Designer Platform, as well as Mentor, Zuken, and Altium flows, accepting a mix of CAD databases where needed for multi-structure design support

Sigrity X SPEEDEM

Sigrity X SPEEDEM technology offers an integrated environment for comprehensive signal, power, EMI, and ESD studies, using layout-based finite-difference time-domain (FDTD) simulations. This innovative tool seamlessly combines circuit and transmission-line simulations with a high-speed, specialized EM field solver to dynamically analyze interactions between signals, power, and ground on IC package and board signals and planes, ensuring rapid, precise results.

  • Workflows also include interconnect model extraction, time domain reflection (TDR), time domain transmission (TDT), and power ripple analysis
  • Unique electromagnetic compliance (EMC) simulation solution with support for non-linear drivers and receivers
  • Determines impact of variations in stack-up, plane geometries, and I/O configurations
  • Observes noise generation, identifies how it propagates, and determines if it stays within targeted levels
  • Interconnect model extraction of single or coupled signal lines for external circuit simulators such as Sigrity SystemSI tool
  • Serves as Sigrity SystemSI FDTD-direct engine for system-level power-aware SI analysis (no requirement for S-parameters)
  • ESD workflow provides feedback on effectiveness of TVS diodes
  • Optimized for flows with Allegro X Design Platform, Allegro X Advanced Package Designer Platform, as well as Mentor, Zuken, and Altium flows, accepting a mix of CAD databases where needed for multi-fabric design support

Sigrity X Starter Kit

The Sigrity Starter Kit offers an easy entry into signal and power integrity, allowing you to quickly identify issues in PCB and IC package layouts using workflows from advanced tools like Sigrity X PowerSI as well as tool outside the portlio like Celsius Studio. With a robust layout workbench, you can import files from popular layout tools and generate detailed reports, making it simple to expand into more advanced analyses as needed.

  • Utilizes the same trusted Sigrity signal and power integrity engines and workflows found in popular advanced tools
  • Generate detailed reports that can be shared with layout teams to correct layout problems causing SI and PI problems
  • All workflows are easily accessible from the unified layout workbench
  • Optimized for flows with Allegro X Design Platform, Allegro X Advanced Package Designer Platform, as well as Mentor, Zuken, and Altium flows

Sigrity X Topology Explorer

Sigrity X Topology Explorer offers a versatile environment for comprehensive what-if analysis of signal and power integrity, utilizing pre-route, measured, or EM-extracted interconnect models. With a user-friendly interface compatible with Sigrity X SystemSI software, it manages complex topologies across multiple boards and packages, providing detailed simulations, waveform analyses, and easily documented results.

  • Versatile topology exploration for what-if analysis of signals, power, or both combined
  • SI/PI analysis using interconnect models that are pre-route, captured from measurement, or extracted using EM tools
  • Familiar user interface compatible with Sigrity SystemSI software, adaptable to any signal, group of signals, or interface

Sigrity X XtractIM

Sigrity X XtractIM technology leverages hybrid electromagnetic (EM) solvers to create accurate RLC, IBIS, or SPICE models over 10 times faster than traditional methods, supporting system-level signal and power integrity simulations with broadband optimization. Its user-friendly workflow simplifies tasks such as stackup checking and signal/power net selection, making it ideal for both casual and frequent users while quickly identifying potential package performance issues.

  • Extracts models for an entire package or only selected nets
  • Creates ball grid array (BGA), system-in-package (SiP), and leadframe package models
  • Supports designs with wirebond and flip-chip die attachment
  • Produces standard IBIS models (with or without coupling)
  • Generates RLGC models with asymmetric PI or T circuits
  • Produces compact broadband models with verifiable full-wave accuracy
  • Examines RLC model values as tables and netlists, or as 2D curves and 3D distributions
  • Assures broadband model compatibility with time-domain circuit simulation
  • Outputs Model Connection Protocol (MCP) and Chip Package Protocol (CPP) for circuit model connection
  • Generates HTML format electrical performance assessment report
  • Optimized for flows with Allegro X Design Platform, Allegro X Advanced Package Designer Platform, as well as Mentor, Zuken, and AutoCAD flows

Sigrity X SystemPI

Sigrity X SystemPI, integrated with Celsius Studio, enables rapid implementation of multi-board or multi-fabric PDN topologies and early power integrity analysis from source to sink. Its flexible topology environment supports what-if scenarios and allows for seamless swapping of PDN models to optimize performance and diagnose design issues efficiently.

  • Utilizes the same trusted Sigrity X power integrity engines found in tools used for layout-based analysis
  • Compatible with PDN models extracted with Sigrity X PowerSI and the Cadence Clarity Studio as well as other interconnect modeling tools
  • Supports die model generation or utilizes die models created with the Cadence Voltus IC Power Integrity Solution
  • Highly automated measurement and reporting capabilities

特征

面向 PCB 和 IC 封装的设计前、设计过程中和设计后信号和电源完整性分析

利用我们为高速电子产品量身定制的全方位解决方案，实现精确的信号和电源完整性分析，在紧迫的工期内顺利交付设计产品。在满足紧迫时间要求的同时确保一流的产品性能和可靠性，显著提高设计效率。

Feature Name Description
Hybrid Solver and Advanced PI Updates Power-aware, high-accuracy SI analysis for leading-edge DDR5 and 112G interfaces, combining advanced interconnect modeling with time-domain simulation for comprehensive SerDes analysis and interface compliance signoff.
Layout Workbench Offering faster interfaces, customizable themes, context-sensitive menus, and unified workflows, all within a single .spd file for enhanced usability and efficiency.
Performance-Drive Results Sigrity X allows for significantly faster and more accurate IC package and PCB simulations, with performance enhancements ranging from 7.18X to 15.1X due to distributed computing and code optimization, all without compromising accuracy.
Signoff Accuracy Catch electrical problems early to deliver on-time, within-budget products using the Sigrity X trusted simulation accuracy and seamlessly leverage electromagnetic (EM) analysis.
Early Signal and Power Integrity Issue Detection Integration into the efficient and accurate Allegro X design flow with visions identifies signal and power integrity issues early, minimizing analysis and layout iterations and accelerating time to market.
Operating System Support Multisystem support with Microsoft Windows and Linux
Interface Databases Interfaces to PCB and IC package layout databases from Cadence, Mentor Graphics, Altium, Zuken, and AutoCAD.
Impedance Analysis Screening The analysis screening feature eliminates the need for SI models, offering a comprehensive global view with intuitive graphic overlays, tables, and plots. Effortlessly sort results to quickly identify and address outliers.
Coupling Analysis Screening The coupling analysis screening quickly scans the design for cases of excessive coupling between signals. A global view of results is provided with graphics, tables, and plots.
Reflection Analysis Leveraging SI models to simulate selected signals, allowing designers to effortlessly sort and analyze results for outliers across various signal quality metrics. Enjoy enhanced capabilities like detailed waveform viewing, batch simulation, insightful tooltips, and the flexibility to use default or custom I/O models.
Crosstalk Analysis The crosstalk analysis feature allows designers to use either default or specific I/O models to identify victim crosstalk nets and individual and worst-case aggressors.
IR Drop Analysis The IR drop analysis feature provides IR drop, absolute voltage, current density, and current view modes. Current vectors, non-deal ground support, and pass/fail constraints are also offered.
PDN Analysis Accurate handling of non-ideal power delivery system influences on SI
Comprehensive Evaluation of SI Effects Concurrently evaluate SI effects such as losses, reflections, crosstalk, and simultaneous switching output (SSO).
Industry Standard File Support SPICE (HSPICE and others), IBIS (native IBIS, BIRD95/98, AMI), S-parameters (Touchstone/Cadence Sigrity Broadband Network Parameter (BNP) syntax), Cadence Sigrity MCP.
Standard Interface Support

Parallel bus interface compliance checks included for DDR2, DDR3, DDR4, LPDDR3, LPDDR4

Serial Link compliance checks included for PCI Express (PCIe) 3.0, PCIe 4.0, SFP+, 10GBASE-KR, HDMI, USB 3.0, USB 3.1, 100BASE-T1
Automated Die-to-Die Signal Integrity (SI) Analysis Source-synchronous for parallel buses, serial links with a focus on SerDes channels, and a general-purpose topology exploration environment for signal, power, or combined what-if analysis—covering DC to over 56GHz (112Gbps) using frequency domain, time domain, and statistical analysis methods.
Develop, test, and utilize IBIS AMI TX and RX Model Development and Testing for Serial Link Analysis.
Reduce costs and time Quantify the bit error rate (BER) and performance of complex SerDes channels.
Parallel Bus Analysis Supports concurrent simulation of high-speed bus interfaces like DDRx memory designs, accounting for dielectric and conductor losses, reflections, ISI, crosstalk, and SSN, which is crucial for emulating real hardware behavior with tight timing margins and comprehensive analysis across chip, package, and board structures.
Serial Link Analysis Serial Link Analysis approach simulates end-to-end channel behavior to produce eye diagrams, bathtub curves, and predict BER performance, while identifying jitter and noise impacts for design improvements, fully supporting IBIS AMI TX and RX models in assessing chip-level signal conditioning and clock/data recovery.
Rapid Model Creation Fast, easy model creation from N-port passive parameters for HSPICE and SPICE simulators.
High-Fidelity Model Generation Generates models for DC through broadband frequencies with high-order, numerically stable responses, and rigorous passivity enforcement.
Comprehensive Structural Modeling Models and extracts network parameters for various structures including IC packages, RF components, PCBs, cables, and connectors, addressing real-world scenarios.
Accurate Model Verification Verifies behavioral model accuracy against the original transistor model with included time domain simulation and accuracy checks during conversion.
User-Friendly Automation Highly automated, wizard-based approach guides users through creating IBIS-AMI models, including all IBIS BIRD95/BIRD98 power-aware effects.
Advanced Visualization and Analysis Provides 2D/3D visualization, plotting, and spreadsheet data management to pinpoint package performance issues and potential risks efficiently.
Comprehensive Interconnect and EMC Analysis Includes interconnect model extraction, TDR, TDT, power ripple analysis, EMC simulation with non-linear driver support, impact assessment of stack-up and plane variations, noise generation observation, system-level power-aware SI analysis, and ESD workflow feedback on TVS diodes effectiveness.
Comprehensive PDN Optimization and Visualization Eliminates decap over-design for PCBs and IC packages, reduces PDN cost, develops effective decap guidelines, identifies EMI decap locations, and provides intuitive visualization of PDN performance with robust hybrid EM/circuit analysis technology.
Full-Wave Accuracy Utilizes full-wave hybrid solvers for RLGC parasitics based on S-parameters, accounting for all physical effects and coupling mechanisms, to generate entire package models from a single simulation.
Comprehensive Package Support Supports various IC package types, including BGA, leadframe, wirebond, and flip-chip for single-die, SiP, and multi-die designs. Extracts models for entire packages or selected nets, incorporating discrete components for accurate power delivery and coupling analysis, crucial for SSO/SSN analysis.

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Next Steps

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