SystemSI – Parallel Bus
When simulating a DDR4 interface in the Sigrity™ SystemSI™ tool, you now have added the ability to validate JEDEC’s DDR4 bit error rate (BER) requirement of 1e-12. This is accomplished by running high-capacity channel simulation on the DDR4 data bus.
System SI Testbench (now System Explorer)
A new general version of the Sigrity SystemSI tool is available to simulate single-ended or differential signals traveling on either single or multiple fabrics. The Sigrity SystemSI testbench can be used as a power-aware topology simulation tool (using IBIS models) that connects interconnect models that are either pre-route or extracted.
Allegro Sigrity PI Base
DRC Markers – IR drop analysis will now create DRC markers. These DRC markers can be loaded into the Allegro® environment to pinpoint the areas that need to be corrected.
Reduced setup time when iterating – When a design is edited and renamed after analysis has been performed, the same setup information can be reused from the previous analysis despite the new .brd file name.