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    • DESIGN EXCELLENCE
    • 数字设计与Signoff
      数字设计与 Signoff 概述

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

      全流程数字解决方案 相关产品 A-Z

      工具目录
      • 逻辑等效性检查
        • Products
        • Conformal Equivalence Checker
        • Conformal Smart LEC
      • SoC Implemenation and Floorplanning
        • Products
        • Innovus Implementation System
        • First Encounter Design Exploration and Prototyping
        • Virtuoso Digital Implementation
      • 形式验证与功能 ECO
        • Products
        • Conformal ECO Designer
      • 低功耗验证
        • Products
        • Conformal Low Power
      • RTL 综合
        • Products
        • Stratus High-Level Synthesis
        • Genus Synthesis Solution
        • Joules RTL Power Solution
        • Virtuoso Digital Implementation
      • 功耗分析
        • Products
        • Joules RTL Power Solution
      • SDC and CDC Signoff
        • Products
        • Conformal Litmus
        • Conformal Constraint Designer
      • 硅签收
        • Products
        • Pegasus Verification System
        • Quantus Extraction Solution
        • Tempus Timing Signoff Solution
        • Assura Physical Verification
        • Physical Verification System
        • CMP Predictor
        • MaskCompose Reticle and Wafer Synthesis
        • QuickView Signoff Data Analysis
        • LDE Electrical Analyzer
        • Process Proximity
        • Pattern Analysis
        • Litho Physical Analyzer
        • Voltus IC Power Integrity Solution
        • Voltus-Fi Custom Power Integrity Solution
      • Library Characterization
        • Products
        • Liberate Trio Characterization Suite
        • Liberate MX Memory Characterization
        • Liberate AMS Mixed-Signal Characterization
        • Liberate LV Library Validation Solution
        • Liberate Characterization Solution
        • Liberate Variety Statistical Characterization
      • 可测性设计
        • Products
        • Modus DFT Software Solution
      • 流程
        • 流程
        • 3D-IC
        • 先进工艺节点
        • 基于 ARM 的设计
        • Library Characterization Flow
        • 低功耗
        • 混合信号
    • 定制 IC/模拟/ RF 设计
      定制 IC /模拟/ RF 设计概述

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

      概述 相关产品 A-Z

      工具目录
      • 电路设计
        • Tools
        • What's New in Virtuoso
        • Virtuoso Schematic Editor
        • Virtuoso ADE Product Suite
      • 电路仿真
        • Tools
        • Spectre Simulation Platform
        • Spectre X Simulator
        • Spectre eXtensive Partitioning Simulator
        • Spectre RF Option
        • Spectre AMS Designer
      • 版图设计
        • Tools
        • What's New in Virtuoso
        • Virtuoso Layout Suite
      • 版图验证
        • Tools
        • Virtuoso DFM
        • Physical Verification System
        • Virtuoso Integrated Physical Verification System
      • 特征库提取
        • Tools
        • Liberate Trio Characterization Suite
        • Virtuoso Liberate MX Memory Characterization Solution
        • Virtuoso Liberate AMS Mixed-Signal Characterization Solution
        • Liberate Variety Statistical Characterization
        • Liberate Characterization Solution
        • Liberate LV Library Validation Solution
      • 流程
        • 流程
        • 电学感知设计(EAD)
        • 先进工艺节点
        • Virtuoso RF Solution
        • Virtuoso System Design Platform
        • 5G Systems and Subsystems
    • 系统设计与验证
      系统设计与验证概述

      Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.

      系统验证套件 相关产品 A-Z

      工具目录
      • 调试纠错分析
        • Tools
        • Indago Debug Platform
        • Indago Debug Analyzer App
        • Indago Embedded Software Debug App
        • Indago Protocol Debug App
        • SimVision Debug
      • 硬件仿真加速器
        • Tools
        • Palladium Z1 Enterprise Emulation System
        • Palladium Dynamic Power Analysis
        • Palladium Hybrid
        • SpeedBridge Adapters
        • Emulation Development Kit
        • Virtual JTAG Debug Interface
        • Accelerated VIP
        • QuickCycles Services
        • VirtualBridge Adapters
      • 形式化验证与静态验证
        • Tools
        • JasperGold Formal Verification Platform (Apps)
        • Assertion-Based Verification IP
      • FPGA 原型验证
        • Tools
        • Protium S1 Desktop Prototyping Platform
        • Protium X1 Enterprise Prototyping Platform
        • SpeedBridge Adapters
      • 验证规划与管理
        • Tools
        • vManager Metric-Driven Signoff Platform
      • 仿真与 Testbench 验证
        • Tools
        • Xcelium Parallel Simulator
        • Incisive Functional Safety Simulator
        • Incisive Specman Elite
      • 软件驱动验证
        • Tools
        • Perspec System Verifier
        • Indago Embedded Software Debug App
        • Virtual System Platform
      • 验证IP(VIP)
        • Tools
        • Accelerated Verification IP
        • Assertion-Based VIP
        • Verification IP (VIP) Catalog
      • 流程
        • 流程
        • 基于 ARM 设计的验证方案
        • 汽车功能安全性验证
        • 基于覆盖率度量的验证签收
        • 混合信号验证
        • 低功耗验证方法学
    • IP
      Cadence IP 主页

      这是一个开放的 IP 平台帮助您的APP驱动的 SoC 实现客户化设计

      了解更多

      工具目录
      • Interface IP
        • IP
        • PCI Express IP
        • CCIX IP
        • USB IP
        • SerDes IP
        • Ethernet IP
        • MIPI IP
        • HD Display IP
      • Denali Memory IP
        • IP
        • NAND Flash IP
        • DDR IP
        • HBM2 IP
        • SD / SDIO / eMMC IP
        • Octal and Quad SPI Flash Controller and PHY IP
      • Tensilica 处理器 IP
        • IP
        • HiFi DSPs for Audio, Voice, and Speech
        • ConnX DSPs for Radar, Lidar, and Communications
        • Vision DSPs for Imaging, Vision, and AI
        • Fusion DSPs for IoT
        • DNA Processor Family for On-Device AI
        • Tensilica Customizable Processors
        • Tensilica Reference Configuration
      • Analog IP
        • IP
        • Analog IP
      • System / Peripherals IP
        • IP
        • 8051 Microprocessor IP
        • System Bus Peripherals
        • Audio Controllers
      • 验证 IP
        • IP
        • Accelerated VIP
        • Assertion-Based VIP
        • Memory Models
        • Simulation VIP
        • Productivity Tools
        • Interconnect Solution
    • IC 封装设计与分析
      IC 封装设计与分析概述

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

      概述 相关产品 A-Z

      工具目录
      • IC 封装设计
        • Products
        • Allegro Package Designer
        • SiP Digital Architect
      • SI/PI 协同分析方案
        • Products
        • Allegro Sigrity SI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity Package Assessment and Extraction Option
        • Allegro Sigrity PI Base
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI 分析点工具
        • Products
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity Speed2000
        • Sigrity SystemSI
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity XtractIM
        • Sigrity XcitePI Extraction
      • 跨平台协同设计与分析
        • Products
        • OrbitIO Interconnect Designer
        • IO-SSO Analysis Suite
      • 流程
        • 流程
        • Cross-Substrate互连
        • IC/封装/PCB协同设计
        • InFO封装技术
        • Sigrity最新技术
        • Virtuoso System Design Platform
        • PDN设计
    • SYSTEM INNOVATION
    • 系统分析
      系统分析概述

      Cadence®系统分析解决方案提供高精度的电磁提取和仿真分析,确保您的系统在不同条件下正常运行。

      概述 相关产品 A-Z

      工具目录
      • Electromagnetic Solutions
        • Tools
        • Clarity 3D全波求解器
        • Sigrity XcitePI Extraction
        • Sigrity XtractIM
        • Sigrity PowerSI
      • Thermal Solutions
        • Tools
        • Celsius Thermal Solver
      • Flows
    • 嵌入式原型验证
    • PCB 设计与分析
      PCB 设计与分析概述

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

      概述 相关产品 A-Z 生态服务搜索

      工具目录
      • 原理图设计
        • Tools
        • Allegro Design Entry Capture/Capture CIS
        • Allegro Design Publisher
        • Allegro Design Authoring
        • Allegro FPGA System Planner
      • PCB 版图设计
        • Tools
        • Allegro PCB Designer
        • OrCAD PCB Designer
      • 库与设计数据管理
        • Tools
        • Allegro ECAD-MCAD Library Creator
        • Allegro EDM Solution
        • Allegro PCB Librarian
        • Allegro Pulse
      • 模拟/混合信号仿真
        • Tools
        • Allegro PSpice Simulator
        • OrCAD PSpice Designer
      • SI/PI 协同分析方案
        • Tools
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity SI Base
        • Allegro Sigrity PI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI 分析点工具
        • Tools
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity SystemSI
        • Sigrity Speed2000
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity PowerSI 3D EM Extraction Option
      • Allegro最新技术
        • Tools
        • Board Layout
        • Schematic Capture
        • Data Management
      • Sigrity最新技术
        • Tools
        • Sigrity 2018 Release
        • Sigrity Tech Tips
      • 流程
        • 流程
        • Multi-Board PCB System Design
        • 产品创建
        • ECAD MCAD 协同设计
        • Allegro Right First-Time Design
        • IO-SSO分析套件
        • 3D System Design Solutions
        • PDN设计
        • LPDDR4 完整分析方案
        • 功耗感知信号完整性分析
        • 接口感知方法
        • Sigrity串行链路分析
    • PERVASIVE INTELLIGENCE
    • Tensilica 处理器 IP
    • 机器学习
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    • INDUSTRIES
    • 5G Systems and Subsystems
    • 航天与国防
    • 汽车电子解决方案
    • TECHNOLOGIES
    • 3D-IC 设计
    • 先进工艺节点
    • Arm 解决方案
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    • 低功耗
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    • 光学
  • 技术服务
    • 技术服务概要

      帮助您实现广泛的商业目标

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    • 设计服务
    • 培训
    • 设计方法学服务
    • 虚拟集成化计算机辅助设计 (VCAD)
  • 支持与培训
    • 技术支持
      支持概要

      24小时全球范围的技术支持。

      了解更多 登录技术支持

      • 支持流程
        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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      • 客户支持联系人
        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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    • 全球培训课程目录
    • Custom IC / Analog / RF Design
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Circuit Design and Simulation
        • Featured Courses
        • Virtuoso ADE Assembler Series
        • Virtuoso ADE Verifier
        • Virtuoso Schematic Editor
        • Mixed Signal Simulations Using AMS Designer
        • Spectre Accelerated Parallel Simulator
        • Additional Courses
      • Electrically-Aware Design
        • Featured Courses
        • Physical Verification System
        • Virtuoso Analog Design Environment
        • Virtuoso Electrically-Aware Design with Layout-Dependent Effects
        • Virtuoso Schematic Editor
        • Quantus QRC Extraction Series
        • Spectre Accelerated Parallel Simulator
      • Infrastructure
        • Featured Courses
        • SKILL Development of Parameterized Cells
        • SKILL Language Programming
        • SKILL Language Programming Introduction
        • SKILL Programming for IC Layout Design
      • Layout Design and Verification
        • Featured Courses
        • Virtuoso Layout Pro Series
        • Virtuoso Space-Based Router
        • Virtuoso Floorplanner
        • Quantus QRC Extraction Series
        • Using Virtuoso Constraints Effectively
        • Virtuoso Connectivity-Driven Layout Transition
        • Physical Verification System
      • Library Characterization
        • Featured Courses
        • Cadence Library Characterization and Validation
        • Spectre Accelerated Parallel Simulator
        • Virtuoso ADE Assembler Series
      • Modeling
        • Featured Courses
        • Analog Modeling with Verilog-A
        • Behavioral Modeling with VHDL-AMS
        • Behavioral Modeling with Verilog-AMS
        • Mixed Signal Simulations Using AMS Designer
        • Real Modeling with SystemVerilog
        • Real Modeling with Verilog-AMS
        • Mixed-Signal IP and Testbench Reuse
      • RF Design
        • Featured Courses
        • Quantus QRC Transistor-Level T1: Overview and Technology Setup
        • Quantus QRC Transistor-Level T2: Parasitic Extraction
        • Quantus QRC Transistor-Level T3: Extracted View Flows and Advanced Features
        • Spectre Accelerated Parallel Simulator
      • Variation Aware Design
        • Featured Courses
        • Virtuoso ADE Assembler S1: Introducing the Assembler Environment
        • Virtuoso ADE Assembler S3: Circuit Checks, Device Asserts, and Reliability Analysis
        • Variation Analysis Using the Virtuoso ADE Assembler
        • Virtuoso Spectre Pro Series
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • Languages and Methodologies
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Assertions
        • Featured Courses
        • Verification with PSL
      • Behavioral Language for AMS Simulation
        • Featured Courses
        • Behavioral Modeling with VHDL-AMS
        • Behavioral Modeling with Verilog-AMS
        • Real Modeling with SystemVerilog
        • Real Modeling with Verilog-AMS
      • Scripting
        • Featured Courses
        • Perl for EDA Engineering
        • Tcl Scripting for EDA
      • Specman and UVMe
        • Featured Courses
        • Specman Advanced Training
        • Specman Fundamentals for Block-Level Environment Developers
      • SystemC
        • Featured Courses
        • C++ Language Fundamentals for Design and Verification
        • SystemC Language Fundamentals
        • SystemC Transaction-Level Modeling (TLM 2.0)
      • SystemVerilog and UVM
        • Featured Courses
        • Real Modeling with SystemVerilog
        • SystemVerilog Advanced Register Verification Using UVM
        • SystemVerilog for Design and Verification
        • SystemVerilog for Verification
      • Verilog and VHDL
        • Featured Courses
        • VHDL Language and Application
        • Verification with PSL
        • Verilog for VHDL Users
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Digital Design and Signoff
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Block and Hierarchical Implementation
        • Featured Courses
        • Analog-on-Top Mixed-Signal Implementation
        • Innovus Implementation System (Block)
        • Innovus Implementation System (Hierarchical)
      • Equivalence Checking
        • Featured Courses
        • Encounter Conformal ECO
        • Logic Equivalence Checking with Conformal EC
      • Silicon Signoff
        • Featured Courses
        • Voltus Power-Grid Analysis and Signoff
      • Synthesis
        • Featured Courses
        • Advanced Synthesis with Genus Stylus Common UI
        • Genus Synthesis Solution with Stylus Common UI
        • Low-Power Synthesis Flow with Genus Stylus CommonUI
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • IC Package Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Cross-Platform Co-Design and Analysis
        • Featured Courses
        • OrbitIO System Planner
        • SiP Layout
      • IC Package Design
        • Featured Courses
        • SiP Layout
      • SI/PI Analysis Integrated Solution
        • Featured Courses
        • Allegro Sigrity PI
        • Allegro Sigrity Package Assessment and Model Extraction
        • Allegro Sigrity SI Foundations
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • SI/PI Analysis Point Tools
        • Featured Courses
        • Allegro Sigrity Package Assessment and Model Extraction
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • PCB Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Analog/Mixed-Signal Simulation
        • Featured Courses
        • Allegro AMS Simulator Advanced Analysis
        • Analog Simulation with PSpice
      • Design Authoring
        • Featured Courses
        • Allegro Design Entry HDL Basics
        • Allegro Design Entry HDL SKILL Programming Language
        • Allegro Design Entry Using OrCAD Capture
        • Allegro System Architect
        • Allegro Team Design Authoring
      • Library and Design Data Management
        • Featured Courses
        • Allegro Design Workbench for Administrators
        • Allegro Design Workbench for Engineers and Designers
        • Allegro Design Workbench for Librarians
        • Allegro PCB Librarian
      • PCB Layout
        • Featured Courses
        • Allegro High-Speed Constraint Management
        • Allegro PCB Editor Basic Techniques
        • Allegro PCB Editor Intermediate Techniques
        • Allegro PCB Router Basics
      • SI/PI Analysis Integrated Solution
        • Featured Courses
        • Allegro Sigrity PI
        • Allegro Sigrity SI Foundations
        • Sigrity PowerSI for Model Generation and Analysis
        • Sigrity PowerDC and OptimizePI
      • SI/PI Analysis Point Tools
        • Featured Courses
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • System Design and Verification
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Emulation and Acceleration
        • Featured Courses
        • Protium Rapid Prototyping Platform
      • Formal Verification
        • Featured Courses
        • JasperGold Formal Fundamentals
        • Verification with PSL
      • Planning and Management
        • Featured Courses
        • Foundations of Metric Driven Verification
        • Metric Driven Verification using Incisive vManager
      • Scripting
        • Featured Courses
        • Perl for EDA Engineering
        • Tcl Scripting for EDA
      • Simulation, Testbench and Debug
        • Featured Courses
        • Xcelium Fault Simulator
        • Incisive Functional Safety Simulator
        • Low-Power Simulation with IEEE Std 1801 UPF
      • Specman and UVMe
        • Featured Courses
        • Specman Advanced Training
        • Specman Fundamentals for Block-Level Environment Developers
      • SystemC
        • Featured Courses
        • C++ Language Fundamentals for Design and Verification
        • SystemC Language Fundamentals
        • SystemC Transaction-Level Modeling (TLM 2.0)
      • SystemVerilog and UVM
        • Featured Courses
        • Real Modeling with SystemVerilog
        • SystemVerilog Advanced Register Verification Using UVM
        • SystemVerilog for Design and Verification
        • SystemVerilog for Verification
      • Verilog and VHDL
        • Featured Courses
        • VHDL Language and Application
        • Verification with PSL
        • Verilog for VHDL Users
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Tensilica Processor IP
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • ConnX DSPs
        • Featured Courses
        • Tensilica ConnX BBE16EP Baseband Engine
        • Tensilica ConnX BBE32EP Baseband Engine
        • Tensilica ConnX BBE64EP Baseband Engine
      • Fusion DSPs
        • Featured Courses
        • Tensilica Fusion F1 DSP
        • Tensilica Fusion G3 DSP
      • HiFi DSPs
        • Featured Courses
        • Tensilica HiFi 2/EP/Mini Audio Engine ISA
        • Tensilica HiFi 3 Audio Engine ISA
        • Tensilica Audio Codec API
      • Tensilica Processors
        • Featured Courses
        • Tensilica Processor Fundamentals
        • Tensilica Instruction Extension Language and Design
        • Tensilica Xtensa Hardware Verification and EDA
        • Tensilica Xtensa Processor Interfaces
      • Vision DSPs
        • Featured Courses
        • Tensilica Vision P5 DSP
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

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  • 供电网络 (PDN) 设计

供电网络 (PDN) 设计

集成Layout设计和仿真分析于一体的约束驱动设计方案

Allegro Sigrity PI Solution 数据手册

使用基于团队协作的方法来进行PCB电源完整性分析以达到更好的效果

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核心优势

  • 基于团队的约束驱动设计流程:由PCB layout专家执行初级PI分析;由此节省下来的时间,使PI专家得以集中精力攻克高级分析任务
  • 自动完成交流(AC)和直流(DC) PI分析设置,并可对设置进行复用,从而轻松便捷地实现更改后的设计分析
  • 使用设计规则检查(DRC)标记和交叉检测,轻松识别可满足PDN特定要求所需的布局、布线更改

在PCB设计中,由于多方因素共同导致了电源完整性问题,因而直流分析至关重要。随着电路的核心电平持续下降,低于1.2V的情况在如今已十分常见。而随着电压的降低,电流的需求则会增加(直流压降= I * R)。电子器件的小型化使得电路板层数减少而密度增加,从而减少了电源网络的可用面积。过孔周围的反焊盘不仅会穿透电路板更会产生重叠,雪上加霜(瑞士奶酪效应)。

此外,PCB设计人员还面临着额外的供电网络(PDN)挑战:首先是来自硬件设计师或电源完整性(PI)工程师的条条指令,这些指令通过电子邮件、电话、经验规则等传达给PCB设计人员。而PCB设计人员则必须将所有这些指示和规则应用于多个供电网络。一经完成,则又将面临新的额外任务——例如: “你能将面积缩小20%吗?” 、“你能去掉两个平面层和五个电容吗?”、以及老生常谈的问题“你能提前完成吗?”

复杂的电路板可能有几十个电源通道、数百个电源网络(包括滤波网络)以及大量构成PDN的组件。对数百页原理图进行整理以确认PDN在逻辑上的连接关系是一大痛点。然而,当在设计过程后端,电源完整性分析要求指定所有网络和组件并为其建模时,一切则是痛上加痛:仅仅完成设置都可能需要花费几天甚至几周的时间。

另一个挑战则是如何沟通设计问题:PI工程师如何向PCB设计人员提出问题并进行指导? PCB设计人员如何与PI工程师沟通解决方案? PCB设计人员如何确定解决方案的可行性?我们的集成功能可帮助PCB设计人员和PI工程师有效解决如上问题。此外,如果PI工程师尚未传达指导意见,PCB设计人员可以使用工具自动完成初级电气约束条件计算,从而顺利开展工作而不必坐等浪费宝贵产品开发时间。

PowerTree图形环境

Cadence Allegro® PowerTree™ Technology允许PCB layout专家和硬件设计师在PDN拓扑结构中以图形方式查看源端/负载端的定义、离散器件的参数值、模型名称、网络名称、去耦电容值以及目标阻抗约束等。

 

硬件设计人员更可以轻松一键实现早期可行性检查分析。通过读取原理图数据,即可确定PDN拓扑结构是否已被正确捕获并符合电源设计标准。

 

通过由硬件设计师和PCB layout专家分担执行简单的分析,PI专家可以由此专注于更专业的分析。PowerTree technology的自动化设置,使得PI专家甚至设计新手们不再花费数天或数周的时间进行PI分析的参数设置。将PowerTree数据应用于物理设计使得仿真变得极为简单,只需几个按钮即可完成任务。

集成功能

去耦电容放置规则要求PI专家进行PI分析之后再确定每个IC的理想去耦方案。此外,PI专家必须创建PI约束集,才能指导PCB设计人员把去耦电容放置在合适的位置上。

 

由PI设计人员的规则所决定的DRC标记被标注在Cadence Allegro PCB Designer中。这些标记使PCB设计人员能够理解PI工程师发现的PDN问题并进行相应处理。

 

Allegro PCB Designer和分析结果之间的交叉检测使PCB设计人员能够使用可视化分析结果来确定PCB中需要改变的内容,例如增加电源铜皮面积的大小、添加过孔、增加电源平面的层数等。

 

复用PI专家的设置可以令PCB设计人员对设计进行修改并再次仿真分析修改后的成果,同时也可对原始设置进行更改。

Allegro / Sigrity集成

Allegro Sigrity™ PI Base集成了Allegro和Sigrity技术,用于PCB、IC封装和系统级封装(SiP)设计的PI分析,并通过集成layout设计和仿真分析于一体实现了约束驱动设计。Allegro Sigrity PI Base的主要优势包括:

  • 可靠的Sigrity分析引擎
  • 从原理图生成的PowerTree数据可自动执行仿真设置
  • 业界首个约束驱动的PI设计流程,可执行去耦电容的选择和布局
  • 直流分析后自动进行layout设计和分析结果之间的交叉检测,可轻松识别并解决物理设计(PCB电路)中的直流压降问题
  • 既能帮助PCB设计工程师有效进行layout设计,又能帮助PI工程师快速进行仿真设置
  • 附加选项可执行进一步的详细分析、合规性分析和评估等

产品演示

使用基于团队协作的方法来进行PCB电源完整性分析以达到更好的效果

开始观看

希捷公司(Seagate Technology) 采用Allegro 和Sigirty 工具,成功减少压降、缩短审核周期并降低生产成本

  • Related Products

    • Sigrity XtractIM
    • Voltus IC Power Integrity Solution
    • Allegro PCB Designer
    • Sigrity PowerDC
    • Allegro Sigrity PI Base
Videos

Sigrity 技术小贴士:PCB设计师如何发现和解决电源完整性问题

Sigrity 技术小贴士:PCB 设计师如何创建初始供电网络限制而无需具备专业电源完整性分析技能

DesignCon 2017: Sigrity 2017 Portfolio Highlights

运用PowerDC技术进行多封装、PCB电热协同仿真

Allegro Sigrity OptimizePI - Automated Decap Design

Sigrity 技术小贴士:如何在 PCB 设计团队内部共享供电网络设计分析

News ReleasesVIEW ALL
  • Cadence Delivers Advanced Packaging Reference Flow for Samsung Foundry Customers 11/13/2018

  • Cadence Delivers Support for TSMC InFO_MS Advanced Packaging Technologies 10/02/2018

  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • New Cadence Virtuoso System Design Platform Provides Seamless Design Flow Between IC, Package and Board 05/30/2017

  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff 01/25/2017

BlogsVIEW ALL
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