Complete Design Flow for Faster PCB Analysis
Memory interfaces are beginning to look like serial links did eight years ago (see related article on DDR4). With LPDDR4 expected to reach 4,266 Mtps, we are bound to see more of the techniques that are used in serial links, such as feed forward equalization (FFE) in the transmitter and adaptive equalization in the receiver that will require algorithmic models for simulations.
Now that JEDEC requires bit-error rate tests, high-capacity simulation with IBIS-AMI models will be required to fully test an LPDDR4 interface. As introduced with our DDR4 solution, a unique integration of serial link channel simulation with our memory interface compliance tests enables millions of bits to be simulated in a short period of time to enable bit-error rate analysis. This gives customers the unique ability to run hundreds of thousands or even millions of bits of traffic through LPDDR4 interfaces, well beyond the capacity of traditional circuit simulation.
The Cadence® Sigrity SystemSI tool is part of the Allegro® Sigrity Power-Aware SI solution that provides a complete design flow though the PCB analysis process.
- Concurrent simulation of reflection, loss, crosstalk, and simultaneous switching output (SSO) effects
- Hybrid solver for efficient S-parameter extraction of large interconnect structures
- 3D full-wave solver for detailed extraction of high-frequency structures
- Comprehensive JEDEC-based post-processing of waveforms for measurement