Latest Vision DSP targeted at always-on and smart sensor applications

The Cadence® Tensilica® Vision P1 DSP is the latest addition to the Vision DSP family. The smallest Vision DSP is targeted for lower power, always-on application offering one-third the power and area compared to the highly successful Vision P6 DSP while offering an easy software transition from Vision P6 DSP via the N way programming model. The Vision P1 DSP also offers flexibility to configure without various features to reduce area and even reduce the data RAM to provide the best area for sensor integration.

Vision P1 Diagram

Key Benefits

Area and Power Optimized

128-bit SIMD with lowest area and power among the Vision DSPs and lower power compared to host CPU and GPU

Vision/Image Processing

Instructions set optimized for computer vision and image processing applications

High Performance

> 0.256TOPS AI performance for object detection, image classification, Image segmentation


  • 256/128b Load/Store capabilities
  • 128 8-bit MAC 
  • 8/16/32-bit fixed-point processing
  • Single-precision (FP32) and half-precision (FP16) floating-point processing
  • Integrated DMA
  • User-defined instructions support
  • Built on LX Xtensa® processor offering best energy efficiency
  • ISO 26262 ready for automotive market


Cadence 通过自身的 Tensilica 处理器 IP 融合了业界领导者的一流产品和服务,可帮助您加快系统级芯片设计的开发,同时达到严苛的功耗和性能要求。浏览下方的 Tensilica 处理器 IP 服务合作伙伴列表。



Cadence 致力于在 Tensilica 处理器系列中实现功能安全应用,无论是现成可用的处理器/DSP IP,还是针对特定应用的、支持定制化的特定域处理器


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