Versatile DSP combining traditional signal processing, codecs and AI functions

The Cadence® Tensilica® HiFi 1 DSP is the smallest and lowest power member of the HiFi DSP family, developed for battery-constrained applications, such as mobile, hearables, wearables, laptop, automotive, and IoT.  Its small area reduces SoC cost. It accelerates AI functions with NN specific ISA and architectural features. It is ideally suited for always-on use cases with sensor fusion or voice/face trigger, along with running codecs and DSP/AI algorithms for pre-processing and post-processing.

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Cycle and Energy optimized for target applications

Sensor Fusion

The HiFi 1 DSP supports sensor fusion concurrent with control and signal processing. It embraces modern algorithms with support for base (light to medium) AI acceleration. Several software partners bring the best sensor fusion software to HiFi1 DSP.

Smallest DSP

The Tensilica HiFi 1 DSP for Audio is the smallest of the HiFi DSP family, reducing SoC cost as well as standby/leakage power.

Lowest Energy DSP

The Tensilica HiFi 1 DSP has the lowest energy consumption of the HiFi DSP family.

Always-On, Always-Listening

The Tensilica HiFi 1 DSP is well-suited to voice trigger, face trigger, and sensor fusion functions that need to be always on, while preserving battery.

Smallest HiFi DSP, Battery-friendly and Cycle-efficient

Always-On Architecture

  • Cycle and energy efficient for Bluetooth and Bluetooth Low Energy (BLE) codecs for speech and music
  • Efficient neural network acceleration ISA and architecture support
  • Efficient fixed-point DSP operations
  • Optional vector floating point unit for easy "Matlab to Optimized DSP" porting
  • Synthesizable over wide frequency range enabling Dynamic Voltage-Frequency Scaling (DVFS) for optimal energy/performance operations

Key Features


VLIW Slots

  • 2

Accumulator Width

  • 64-bit
Fixed-Point MACs per Cycle  32x32
  • 1
32x16
  • 2
16x16/8x8
  • 4

FPU (integrated, optional)

  • Single-precision, two-way Vector FPU with low latency

Instructions for NN

  • Yes

Arithmetic Encoding/Decoding

  • Yes
AVS (Huffman and bitstream operation)
  • Yes

Conditionals

  • Energy-Efficient Vector Boolean Register

Coremark

  • 4.99

User-Defined Instructions

  • Yes

合作伙伴

Cadence 通过自身的 Tensilica 处理器 IP 融合了业界领导者的一流产品和服务,可帮助您加快系统级芯片设计的开发,同时达到严苛的功耗和性能要求。浏览下方的 Tensilica 处理器 IP 服务合作伙伴列表。

技术

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Tensilica 处理器技术

差异化,缩短上市时间,增加灵活性,获得最佳的性能、功率和面积

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TIE

为了优化性能,提高能效,实现差异化,可以对您的DSPs/处理器进行定制

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开发工具链

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Support

Cadence is committed to keeping design teams highly productive with a range of support offerings and processes designed to keep users focused on reducing time to market and achieving silicon success.

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