The Cadence® IP for 10Gbps Multi-Protocol PHY IP is a lower active and low leakage power design crafted for mobile, IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on a single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII specifications. The PCS complies with the PIPE 4.x interfaces and supports dynamic equalization features of different protocols.
Multi-Protocol with Multi-Link Capability
Single-PHY macro offers optimum SoC configurability with the protocol mix and match
Optimized Performance, Power, and Area
Best fit for the application's required performance with small footprint
Comprehensive Test Feature Enables Rapid SoC Development
Extensive BIST and DFT enable ease of integration, faster bring-up, and quick debugging