MIPI DSI TX Controller

MIPI DSI Transmitter

Compliant with the MIPI^® Alliance Specification for Display Serial Interface (DSI^sm), the Cadence^® TX Controller IP for DSI provides the interface from a host device graphics controller to one or more display modules and includes an arbitration layer for arbitrating among the various data and command streams, a DSI protocol layer for protocol functions, and a lane management layer (LML) to distribute the DSI data stream across the active D-PHY^sm lane modules.

MIPI DSI Tx Controller Block Diagram