The Cadence® Denali® PHY and Controller for LPDDR5/4X/4/3 is a family of high-speed on-chip memory interface IP satisfying high-performance requirements with products that are optimized for each application's needs. The Denali LPDDR Controller delivers a wide array of capabilities to address emerging LPDDR DRAM subsystem RAS, ECC, parity, and data-scrubbing functions. The application-optimized LPDDR5 PHY and Controller can achieve industry-leading data rates. Low-power features include multiple low-power states for longer battery life and greener operation.

LPDDR5 PHY IP Write Eye Diagram
LPDDR5 IP Silicon Testing

Key Benefits

Low Latency

For data-intensive applications

Low Power and Area

Industry-leading PPA based on advanced architecture and implementation


Maximum system margin with advanced clocking and I/O architectures


  • Application-optimized configurations for fast time to delivery and lower risk
  • Low-power VDD idle, VDD light sleep, and power-efficient clocking in low-speed modes
  • I/O pads with impedance calibration logic and data-retention capability
  • Fine-grain custom delay cell for delay tuning
  • Internal and external datapath loop-back modes
  • RX and TX equalization for heavily loaded systems
  • Programmable per-bit (PVT compensated) deskew on read and write datapaths
  • Memory controller interface complies with DFI standard up to 5.0
  • Application-optimized configurations for fast time to delivery and lower risk
  • Sideband and in-line SEC/DED ECC
  • Supports advanced RAS features including error scrubbing, parity, etc.
  • Compliant to LPDDR5/4X/4/3 protocol memories
  • Priority per command on Arm®AMBA® 4 AXI, AMBA 3 AXI
  • Single and multi-port host interface options
  • QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces
  • Silicon-proven and shipping in volume