HBM2E/HBM2 PHY and Controller | Cadence

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Overview

The Cadence^® Denali^® HBM2E/2 PHY and Controller IP is silicon-proven and includes architectural improvements drawn from previous-generation DDR5 and LPDDR4 PHYs, achieving breakthrough performance, low energy per bit, and low area relative to the data bandwidth. It is engineered to quickly and easily integrate into SoCs and is verified as part of a complete memory subsystem solution. The HBM2E/2 PHY and Controller IP is an ideal solution for artificial intelligence (AI), high-performance computing (HPC), and image processing applications.

hbm2e-hbm2-phy-controller

Key Benefits

Proven

Silicon characterization reports available

Low Latency

For data-intensive applications

High Performance

Increased data integrity from error correction and optimized throughput of unique pseudo-channel interleaving

Low Power and Area

Low-power control and advanced low-power modes with power down and self-refresh

Features

PHY
Controller

Advanced clocking architecture minimizes clock jitter
DFI PHY Independent Mode for initialization and training
IEEE 1500 interface, Memory BIST feature, and loop-back function
Designed for optimized interposer routing
Programmable per-bit (PVT compensated) deskew on read and write datapaths

High-performance command queue placement and command execution selection
Optimized throughput of unique pseudo-channel interleaving
Lowest latency for data-intensive applications
Low-power control and advanced low-power modes with power-down and self-refresh
Memory controller interface is based on DFI 5.0
DFI frequency ratio of 2:1
Memory BIST feature

Videos

Dual Channel DIMMs for Server Applications

Introducing the DFI 5.0 Interface Standard

Can You Really Reduce DDR Power Dissipation by Reducing the Frequency?

Using DDR PHY Power Features to Reduce Power Dissipation

The 3 Methods of Memory Controller Port Arbitration

Error Correction Code Implementations in Memory Controller Designs

Unpacking the DFI Low-Power Interface

LPDDR4X DRAM: Performance and Power Efficiency Improvements Over LPDDR4

What to Expect from TLM 2.0 Models for Memory Subsystems - Part 1

What to expect from TLM 2.0 Models for Memory Subsystems - Part 2

Introduction to the NVDIMM Standard

Resources

brochure

PHY IP for HBM2 for Samsung 10LPP

White Paper

Emergence of Segment-Specific DDRn Memory Controller and PHY IP Solution

Brochure

PHY IP for HBM2E for Samsung 8LPP

News ReleasesVIEW ALL

Cadence GDDR6 IP Family Is Silicon Proven for TSMC N6 and Immediately Available for Both N6 and N7 Process Technologies 10/07/2020

Cadence Announces Complete, Silicon-Proven LPDDR5 IP Solution 03/04/2019

Cadence Announces Tapeout of GDDR6 IP on Samsung's 7LPP Process, Enabling Complete GDDR6 IP Solution 11/20/2018

How We Developed and Tested a Prototype DDR5 Interface

5/1/2018 Marc Greenberg

LPDDR5 Next Gen High-Performance Low Power Memory Interface

4/2/2019 Kostadin Gitchev

Get Introduced to the DFI 5.0 Specification

5/2/2018 MeeraC

GDDR6 and HBM2E on Samsung Foundry – the SAFE Choice

10/28/2020 Paul McLellan

HBI, a New Standard to Connect Your Chiplets

12/11/2020 Paul McLellan