GDDR6 PHY and Controller IP | Cadence

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Overview

Cadence^® Denali^® silicon-proven GDDR6 PHY and controller IP showcase leading-edge BER, BIST, and RAS capabilities. GDDR6 offers significantly more performance than the fastest speed of DDR5 at a moderate cost, making it ideal for high-bandwidth applications. Cadence’s unique, single-vendor GDDR6 IP solution speeds up integration and reduces interoperability risk.

Key Benefits

Proven

Silicon characterization reports available in multiple process technologies and foundries

Low Latency

For data-intensive applications

Low Power and Area

Industry-leading PPA based on advanced architecture and implementation

Low BER

Supporting standard PCB materials

Reliable

Maximum system margin with advanced clocking and I/O architectures

Future proof

Cutting edge technology with the latest GDDR protocols and the highest data rates

Features

PHY
Controller

Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
DFI PHY Independent Mode for initialization and training
Adaptive and continuous timing recovery
Internal and external datapath loop-back modes
Transmit crosstalk cancelation of immediate neighbors
Per-bit DFE, CTLE, and FFE equalization

In-line SEC/DED ECC
Supports advanced RAS features including error scrubbing, parity, etc.
Compatible with GDDR6 devices compliant to JESD250b
Single and multi-port host options for Arm^® AMBA^®4, AMBA 3 AXI, and low-latency Denali interfaces
QoS features allow command prioritization
Flexible paging policy
Memory controller interface is based on DFI 5.0
The controller runs at 1/8 of the memory clock speed for ease of timing closure

Videos

Dual Channel DIMMs for Server Applications

Introducing the DFI 5.0 Interface Standard

Can You Really Reduce DDR Power Dissipation by Reducing the Frequency?

Using DDR PHY Power Features to Reduce Power Dissipation

The 3 Methods of Memory Controller Port Arbitration

Error Correction Code Implementations in Memory Controller Designs

Unpacking the DFI Low-Power Interface

LPDDR4X DRAM: Performance and Power Efficiency Improvements Over LPDDR4

What to Expect from TLM 2.0 Models for Memory Subsystems - Part 1

What to expect from TLM 2.0 Models for Memory Subsystems - Part 2

Introduction to the NVDIMM Standard

Resources

datasheet

Denali Controller IP for GDDR6

Datasheet

Denali High Speed GDDR6 PHY IP TSMC 6nm/7nm

Datasheet

GDDR6 PHY IP for Samsung 7nm/14nm

News ReleasesVIEW ALL

Cadence GDDR6 IP Family Is Silicon Proven for TSMC N6 and Immediately Available for Both N6 and N7 Process Technologies 10/07/2020

Cadence Announces Complete, Silicon-Proven LPDDR5 IP Solution 03/04/2019

Cadence Announces Tapeout of GDDR6 IP on Samsung's 7LPP Process, Enabling Complete GDDR6 IP Solution 11/20/2018

How We Developed and Tested a Prototype DDR5 Interface

5/1/2018 Marc Greenberg

LPDDR5 Next Gen High-Performance Low Power Memory Interface

4/2/2019 Kostadin Gitchev

Get Introduced to the DFI 5.0 Specification

5/2/2018 MeeraC

GDDR6 and HBM2E on Samsung Foundry – the SAFE Choice

10/28/2020 Paul McLellan

HBI, a New Standard to Connect Your Chiplets

12/11/2020 Paul McLellan