DDR5, DDR4, DDR3 PHY and Controller | Cadence

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Overview

Cadence^® Denali^® DDR solutions, a family of high-speed on-chip interface IP, are leading the way for high-performance computing (HPC) systems and data center applications. The DDR PHY IP is engineered to quickly and easily integrate into any system-on-chip (SoC) and is verified with the Denali DDR Controller IP as part of a complete memory subsystem solution. Available as a product optimized solution for specific applications such as DDR5, DDR4, DDR3 with many configuration options to select desired features and integration aspects.

ddr-lpddr-phy-controller

Key Benefits

Low Latency

For data-intensive applications

Low Power and Area

Industry-leading PPA based on advanced architecture and implementation

Reliable

Maximum system margin with advanced clocking and I/O architectures

Features

PHY
Controller

DDR5/4/3 training with write-leveling and data-eye training
Optional clock gating available for low-power control
Internal and external datapath loop-back modes
I/O pads with impedance calibration logic and data retention capability
Programmable per-bit (PVT compensated) deskew on read and write datapaths
RX and TX equalization for heavily loaded systems

Sideband and in-line SEC/DED ECC
Supports advanced RAS features including error scrubbing, parity, etc.
Compliant to LPDDR5/4X/4/3 and DDR5/4/3 protocol memories
Memory controller interface complies with DFI standards up to version 5.0
Priority per command on Arm^® AMBA^® 4 AXI, AMBA 3 AXI
Single and multi-port host interface options
QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces
Silicon proven and shipping in volume

Videos

Dual Channel DIMMs for Server Applications

Introducing the DFI 5.0 Interface Standard

Can You Really Reduce DDR Power Dissipation by Reducing the Frequency?

Using DDR PHY Power Features to Reduce Power Dissipation

The 3 Methods of Memory Controller Port Arbitration

Error Correction Code Implementations in Memory Controller Designs

Unpacking the DFI Low-Power Interface

LPDDR4X DRAM: Performance and Power Efficiency Improvements Over LPDDR4

What to Expect from TLM 2.0 Models for Memory Subsystems - Part 1

What to expect from TLM 2.0 Models for Memory Subsystems - Part 2

Introduction to the NVDIMM Standard

Resources

datasheet

Denali Controller IP for DDR

LPDDR5/4X/4/3 and DDR5/4/3L/3, to 6400Mbps and beyond

Brochure

DDR5/4 PHY IP for TSMC 7nm

Brochure

Denali DDR PHY IP for TSMC

Brochure

DDR5/4 PHY IP for Samsung 7nm

News ReleasesVIEW ALL

Cadence GDDR6 IP Family Is Silicon Proven for TSMC N6 and Immediately Available for Both N6 and N7 Process Technologies 10/07/2020

Cadence Announces Complete, Silicon-Proven LPDDR5 IP Solution 03/04/2019

Cadence Announces Tapeout of GDDR6 IP on Samsung's 7LPP Process, Enabling Complete GDDR6 IP Solution 11/20/2018

How We Developed and Tested a Prototype DDR5 Interface

5/1/2018 Marc Greenberg

LPDDR5 Next Gen High-Performance Low Power Memory Interface

4/2/2019 Kostadin Gitchev

Get Introduced to the DFI 5.0 Specification

5/2/2018 MeeraC

GDDR6 and HBM2E on Samsung Foundry – the SAFE Choice

10/28/2020 Paul McLellan

HBI, a New Standard to Connect Your Chiplets

12/11/2020 Paul McLellan