The Cadence UCIe PHY is a high-bandwidth, low-power and low-latency die-to-die solution that enables multi-die system in package integration for high performance compute, AI/ML, 5G, automotive and networking applications. The UCIe physical layer includes the link initialization, training, power management states, lane mapping, lane reversal, and scrambling. The UCIe controller includes the die-to-die adapter layer and the protocol layer. The adapter layer ensures reliable transfer through link state management and parameter negotiation of the protocol and flit formats. The UCIe architecture supports multiple standard protocols such as PCIe, CXL and streaming raw mode.

Package Substrate diagram

Key Benefits

Package Flexibility

Supports standard package (2D) and advanced package (2.5D)

Power Efficiency

Advanced architecture meets ultra-low power requirements

Low Latency

For data-intensive applications

High Performance Reliability

Efficient design for maximum die-to-die throughput and link data integrity

Multi-protocol Solution

Supports PCIe, CXL, and streaming protocols


KGD and robust test methods ensure seamless link reliability


  • Supports up to 16Gbps per pin including 4/8/12Gbps
  • SerDes and DDR architecture
  • Forwarded clock, track, and valid pins
  • Sideband messaging for link training and parameter exchange
  • KGD (Known Good Die) testing capability
  • Redundant lane repair (advanced)
  • Width degradation (standard)
  • Lane reversal
  • 2-25mm wide range channel reach
  • Low raw BER 1e-27
  • Lowest latency controller for data intensive die-to-die applications
  • Supports single and multiple PHY modules
  • PCIe, CXL, and streaming protocols
  • CRC and retry mechanism
  • Sideband messaging for link training and parameter exchange
  • Link State Management
  • Parameter Negotiation


UCIe is the Universal Chiplet Interconnect Express, a type of die-to-die (d2d) serial interconnect.