Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Enhanced route planning, optimization, and auto-interactives to quickly design complex, critical interconnect, including high-speed interfaces and buses in IC package design
- Improves substrate yield and prevents manufacturing and assembly issues with full access to DesignTrue DFM and assembly rule checks
The SiP Layout Option enhances the capabilities of Allegro® Package Designer Plus to design high-performance and complex packaging technologies. It adds a powerful set of auto-interactive flow, routing, and tuning features that speed planning, optimizing, routing, and timing closure of critical interconnects such as DDR, high-speed serial, silicon substrate, or graphic interfaces. Intelligent route flow planning and automated breakout tools reduce time-consuming and tedious manual breakout and routing tasks and optimize large bus routes to use minimum space and layers.
With the SiP Layout Option, you can expand your access to our DesignTrue DFM technology. Take advantage of the full suite of DesignTrue DFM real-time manufacturability checks and assembly rules to improve your substrate yield and prevent manufacturing and assembly issues. The option supports the assessment of manufacturing variation and the creation of design variants with different substrate stack-up, die stacking, and wire-bond configurations derived from the same master design. It also enables a bi-directional flow with the Virtuoso® platform for IC/package co-design.
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview