Allegro Package Designer Plus

核心优势

用于单芯片和多芯片引线键合，倒装芯片和晶圆级芯片封装，硅中介层，芯片堆叠以及其他高级封装技术的完整的从前端到后端的物理设计全流程
基于芯片/封装级优化的有效及芯片级IP保护的分布式协同设计
约束驱动的基板互连设计，提取，建模和信号完整性分析

Cadence^® Allegro^® Package Designer Plus能够实现约束驱动的设计校正的封装基板布局。它支持用于单芯片和多芯片BGA / LGA封装设计的完整的从前端到后端的物理实现流程。提供了一组针对特定封装特性的强大功能，例如动态库开发，连接生成/优化，多层引线键合，协同设计，管芯堆叠和TSV，嵌入式腔体，推式布线，报告和量产输出。

Allegro Package Designer Plus 用户界面

系统设计集成

Allegro Package Designer Plus与Cadence OrbitIO™系统规划全集成，可提供完整的封装物理设计功能，以帮助您更早地，更有信心地进行战略权衡。该工具还提供与Cadence Sigrity™，Clarity™和Celsius™分析技术的直接接口，提供集成的布局和分析流程，几乎支持所有先进的IC封装技术，例如复杂的引线键合，铜柱，FOWLP，2.5D，3D ，BGA和PoP。

主要功能

具有实时校正的数据库，物理设计规则和电气约束的实时DRC的单芯片和多芯片封装的优化物理布局解决方案
约束驱动的“一推一推”交互式布线，自动交互和全自动布线
提供复杂的设计规则和电气约束驱动布局
灵活的模型连接，支持网表，原理图和“实时”连接
包括核心DesignTrue DFM规则检查法
可视化并执行3D引线和设计规则检查

Allegro Package Designer Plus 3D界面

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Allegro Package Designer Plus

核心优势

系统设计集成

主要功能

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