Virtuoso System Design
Platform

The Cadence^® Virtuoso^® System Design Platform links two world-class Cadence technologies—custom IC design and package/PCB design/analysis—creating a holistic methodology that automates and streamlines the design and verification flow for multi-die heterogeneous systems.

Leveraging the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment, it provides a single platform for IC-and package/system-level design capture, analysis, and verification. In addition, the Virtuoso System Design Platform  provides an automated bidirectional interface with the Cadence SiP-level implementation environment and Clarity 3d Solver. 

The Virtuoso System Design Platform allows IC designers to easily include system-level layout parasitics in the IC verification flow, enabling time savings by combining package/board layout connectivity data with the IC layout parasitic electrical model. The automatically generated “system-aware” schematic that results can then be easily used to create a testbench for final circuit-level simulation. The Virtuoso System Design Platform automates this entire flow, eliminating the highly manual and error-prone process of integrating system-level layout parasitic models back into the IC designer’s flow.

Integrated Heterogeneous Devices

Many of today’s analog, RF, and mixed-signal designs require the integration of multiple ICs across varying substrate technologies to achieve required performance goals. The integration of heterogeneous devices allows designers to achieve results that can’t easily be duplicated using a monolithic IC (SoC) design approach. At the same time, heterogeneous integration introduces a whole new set of challenges for today’s designers.

System in a package (SiP) is one of the most common methods of integrating mixed technologies into a single design. This approach requires seamless integration between the IC and package substrate design teams and an integrated tool flow. The Virtuoso System Design Platform addresses these challenges with a novel, cross-platform solution that streamlines and automates the design of a package/module featuring off-chip devices and multiple ICs based on differing process design kits (PDKs). 

Features

• Single hierarchical schematic captures IC- through package-level logic, resulting in an automated layout-versus-schematic (LVS) verification flow
• IC verification methodology seamlessly generates testbench-ready schematics that include system-level layout parasitic data taking the guesswork out of electrical signoff  
• Built-in, accurate, and fast 3D EM modeling of package-level passive devices that further streamline the IC verification flow
• Powerful and flexible implementation technology supporting all types of advanced packaging technologies