Stratus High-Level Synthesis | Cadence

overview

Cuts IP Development from Months to Weeks

With Cadence^®Stratus™ High-Level Synthesis (HLS), engineering teams can quickly design and verify high-quality RTL implementations from abstract SystemC™, C, or C++ models. The models can be easily created using the Stratus integrated design environment (IDE). Stratus synthesizable IP for SystemC provides simulation and synthesis models for common bus-based and point-to-point communication protocols as well as common mathematical operations and datatypes.

Leveraging the Genus™ Synthesis and Joules™ RTL Power engines inside of Stratus HLS, the power, performance, and area (PPA) results are typically equal to or better than those achieved with hand-coded RTL. Front-end designers get high-quality PPA estimates through turnkey integration with the Cadence digital flow.

With Stratus HLS, SystemC models can be retargeted to new technology platforms and reused more easily than traditional hand-coded RTL. The Stratus graphical user interface (GUI) and Tcl API also allow designers to quantitatively evaluate tradeoffs between the PPA from within the high-level synthesis environment.

Stratus HLS automates the design and verification flow of hundreds of blocks from transaction-level modeling (TLM) to gates. In addition, Stratus HLS helps with the real-world issues of engineering change orders (ECOs) and routability, both of which normally occur much later in the flow, through tight integration with the full Cadence tool flow.

Users have reported productivity as high as 2 million verified gates/designer/year, compared to 200,000 with the traditional RTL flow. For more details, read the Stratus HLS datasheet.

stratus-hls-diagram

Key Benefits

Enabling a Faster Path to Verified, High-Quality RTL Implementations from Abstract SystemC, C, or C++ Models

Superior PPA

Stratus HLS gives engineering teams the ability to explore hundreds of micro-architectures in a fraction of the time it takes to write and verify a single RTL description. With automated exploration and optimization, designers can quickly find the most optimal implementation.

Ease of Technology Re-Targeting

Stratus HLS starts with transaction-level SystemC, C, or C++ descriptions. Because the micro-architecture details are defined during HLS, the source description is significantly easier to write and re-target, making your IP significantly more portable across different technologies.

Productivity

Stratus HLS is highly productive and can be used interactively or via batch runs controlled via Tcl scripts. Users can define a range of constraints and automatically run high-level synthesis and adjacent tools like simulation, power analysis, and logic synthesis.

customer success

Learn how our customers use Stratus HLS to easily explore and optimize power, performance, and area while accelerating their IP development process.

Designing an Automotive Graphics Display Controller with Stratus HLS

Tim Papenfuss Design Engineer, Socionext

A High Level Synthesis (HLS) Design Flow for Scaling to Multiple IP, SoC, and Process Targets

Hans Yeager, Principle Engineer, Qualcomm Data Center Technologies, Inc.

High-Level Synthesis will supercharge your IP development

Elad Litman, Intel

Design implementation of technology IP using High-Level Synthesis

Rajat Dhawan Engineer, Senior Staff Qualcomm Technologies, Inc

Coverage Closure for HLS-Based Design IP

Krishna Thottempudi Engineer, Senior Staff Qualcomm Technologies, Inc.

Latency-Constrained Design for a Display Stream Compression Decoder with Stratus HLS

Tim Papenfuss Socionext Europe GmbH

HLS enables ML-assisted Architectural Exploration

Bob Condon, PESG Intel

0-60 in 2 seconds: Accelerating an AI chip startup with Cadence-Hosted Design Solutions

David Garrett, VP Hardware, Syntiant Corp

High-Level Synthesis will supercharge your IP development

Matt Bone, Intel

Designing a “First-Time-Right” Wi-Fi HaLow Baseband in less than 6 Months

Stefan Stanic, ASIC Hardware IP Design Engineer Methods2Business

Entering the world of High-Level Synthesis - What we have learned and experienced

High-Level Synthesis Models in Pre-Silicon Verification

Rauf Salimi, Peter Plechinger, Intel

Resources

UCLA leverages high-level synthesis to make rapid architecture trade-offs

Stratus-Joules Solutions: Achieving Energy-Efficient Allocation

EEJournal Chalk Talk: TensorFlow to RTL with High-Level Synthesis

Whiteboard Wednesdays - Low-Power SoC Design with High-Level Synthesis

Whiteboard Wednesdays - TensorFlow to RTL with High-Level Synthesis

Designing an Automotive Graphics Display Controller with Stratus HLS

From TensorFlow to RTL in three months

0-60 in 2 seconds: Accelerating an AI chip startup with Cadence-Hosted Design...

A High Level Synthesis (HLS) Design Flow for Scaling to Multiple IP, SoC, and...

white paper

System-Driven PPA for Multi-Chiplet Designs

White Paper

How High-Level Synthesis Was Used to Develop an Image-Processing IP Design from C++ Source Code White Paper

White Paper

Using High-Level Synthesis to Design and Verify 802.11ah Baseband IP White Paper

Presentation

High-Level Synthesis Will Supercharge Your IP Development

Related products

Genus Synthesis Solution

Provides 3X-5X faster synthesis runtime, scalability to 10M+ instances flat, tight correlation to placement and routing, and globally focused, physically aware early PPA optimization to boost RTL designer productivity

Joules RTL Power Solution

Delivers RTL power estimation accuracy to within 15% of signoff power and up to 20X faster time-based power