WEBINAR
AI Accelerator Design
with Stratus™ HLS
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Key Benefits
- 通过更高级别的抽象，提高效率
- 通过高级优化和探索，提高结果质量
- 通过使用行为 IP，实现更广泛的 IP 重用
Cadence® Stratus™ High-Level Synthesis (HLS) 是首个面向整个系统级芯片(SoC)设计的高级综合平台，与传统 RTL 设计相比，可提供高达 10 倍的效率。Stratus 工具依托超过 14 年的生产 HLS 部署经验，使您可以从 SystemC、C 或 C++ 抽象模型快速设计和验证高质量的 RTL 实现。使用该平台，您可以将知识产权 (IP) 开发周期从数月缩短至几周。
使用 Stratus HLS，您可以使用其集成设计环境 (IDE) 轻松创建抽象模型，并从这些模型综合经过优化的硬件。然后，您可以将这些模型重新定向到新技术平台然后进行重用，这要比传统手动编码的 RTL 更加容易。您可以在 HLS 环境中主动权衡功耗、面积和性能。
用户反应他们的工作效率从传统 RTL 流程的 20 万验证门/设计人员/年，提高至 200 万验证门/设计人员/年。要获取更多详情，请查看 Stratus HLS datasheet。
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相关产品
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相关链接
- Case Study: Blu Wireless Boosts SystemC Design and Verification Productivity Using High-Level Synthesis Technology White Paper
- How the Productivity Advantages of High-Level Synthesis Can Improve IP Design, Verification, and Reuse White Paper
- Using High-Level Synthesis to Design and Verify 802.11ah Baseband IP White Paper
- How High-Level Synthesis Was Used to Develop an Image-Processing IP Design from C++ Source Code White Paper
Customers
With our high-level synthesis flow and the Stratus platform, we're now doing the kinds of things that we couldn't have imagined doing previously.
Ray McConnell, CTO, Blu Wireless Technology
Our highly integrated 100Gbps transport systems operate at very high frequency, which presented a major design challenge. By designing at a higher level of abstraction in SystemC, our design team was able to implement the customized hardware much more quickly and effectively.
Masao Nakano, Design Engineer, Device Development Department, Network Products Division, Fujitsu Kansai-Chubu Net-Tech
Using [the] HLS design flow we got an average 35% better performance with up to 51% less power and up to 38% less area than hand-edited RTL.
Masato Tatsuoka, Socionext Inc.
Training
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview
