Synthesis

Creating the best balance of power, performance, and area (PPA) with increasingly complex requirements and shorter design schedules requires design teams to leverage a sophisticated mix of technologies. Cadence^® synthesis solutions provide an integrated flow that balances the growing need to understand the architectural-level abstraction of the design alongside the detailed physical implementation constraints.

To achieve a 10-fold leap in productivity, many system design and verification engineers are now designing at a higher level of abstraction above RTL. Using Cadence high-level synthesis (HLS) technology, teams can automatically generate high-quality RTL code for their application with as little as 10% of the manual effort.

HLS-generated RTL, hand-written RTL, or acquired soft IP must account for the uncertainties surrounding the effects of the physical interconnect on design convergence during synthesis to provide optimal results. Cadence’s power solution delivers accurate RTL average and time-based power analysis, enabling PPA trade-offs at the earliest stages of the design where the impact of architectural and micro-architectural decisions is the greatest. With optimized RTL in hand, Cadence RTL synthesis technology is fast, scalable, and tightly correlated to place and route.

Stratus High-Level Synthesis

Provides the first HLS platform that you can use across your entire SoC design. Lets you quickly design and verify high-quality RTL implementations from abstract SystemC, C, or C++ models, providing 10X better productivity than traditional RTL design and reducing IP development cycle from months to weeks.

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Genus Synthesis Solution

Provides 3X-5X faster synthesis runtime, scalability to 10M+ instances flat, tight correlation to placement and routing, and globally focused, physically aware early PPA optimization to boost RTL designer productivity.

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Joules RTL Power Solution

Delivers RTL power estimation accuracy to within 15% of signoff power and up to 20X faster time-based power. Measures power on gate-level netlists as well. Provides a unified power calculator that ensures correlation of power results throughout the design flow. The solution is seamlessly integrated with Cadence’s Palladium^® and Incisive^® platforms to help meet system-level power requirements.

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