First Encounter Design Exploration and Prototyping

Cadence^® First Encounter^® technology enables quick full-chip virtual prototyping to accurately capture downstream physical/electrical impacts at the beginning of the design cycle. Its unique partitioning and budgeting capabilities combined with gigaflex technology makes hierarchical implementation easier and faster for giga-scale, high-speed designs.

Accommodating today’s chip design requirements within narrow market windows has led to a predictability crisis. How can engineers determine design feasibility for larger, higher-performance, power-hungry chips with an incomplete netlist, library, and constraints? And how can they quickly assess floorplans for congestion, timing, and power without having to go into real implementation? 

First Encounter technology addresses these challenges from silicon virtual prototyping, automatic floorplanning, and physical synthesis to hierarchical controls for partitioning and budgeting, legal macro and standard cell placement, and complete power-grid design and optimization. The solutions also address hierarchical clock synthesis for high-performance, complex 100M+ instance designs. With such comprehensive capabilities, First Encounter technology helps customers meet their time-to-market requirements confidently, and with significant performance and productivity gains.