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Tempus Timing Signoff Solution

Industry’s fastest-adopted and trusted timing signoff solution for FinFET designs

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The Cadence® Tempus™ Timing Signoff Solution is the industry’s most trusted static timing analysis (STA) tool for FinFET designs. It is the fastest STA tool in the industry with unique distributed processing and cloud capabilities scaling to hundreds of CPUs to quickly complete even the largest designs.

With full foundry certification and a comprehensive set of advanced capabilities, the cloud-ready Tempus solution delivers SPICE-accurate results to hundreds of customers across a broad range of design types, from the high-performance designs to high-volume mobile designs, and mixed-signal chips on mature processes.

More than just an analysis tool, the Tempus solution is also deeply integrated with the Cadence Innovus™ Implementation System, Quantus™ Extraction Solution, and Voltus™ IC Power Solution.

Key Benefits

  • Industry’s fastest runtimes on a single machine or in the cloud
  • 5X faster runtime with CMMMC technology
  • Fully certified down to 3nm
  • Streamline flow development and simplify user trainings with new common user interface shared across the Cadence digital full flow
  • Accurate modeling of ultra-low voltage effects below 0.5V with advanced SI and SOCV, supports both Cadence SOCV library format and Liberty Variation Format (LVF)
ASK US A QUESTION

 

Tempus diagram

Design Robustness

Cadence is focused on innovating in partnership with the industry’s most advanced companies to create even-greater design advantage and shorten time to market with best-in-class power, performance, and area (PPA).

One key aspect of interest to our customers is design robustness and its tradeoff with PPA. Design robustness is a six-prong approach to providing the highest quality of designs via Cadence’s suite of analysis tools—namely ultra-low Vdd robustness, aging robustness (aging-aware STA),voltage robustness (Tempus Power Integrity solution), process robustness (timing robustness), VT robustness, and interconnect robustness.

  1. Aging-Aware STA with Liberate Characterization Solution

    High-reliability semiconductor applications such as automotive and defense must operate predictably over long timespans. To ensure high reliability, designers require accurate analysis of device performance over time without relying on pessimistic margining techniques that negatively impact PPA. To solve this problem, our unified flow, starting from Liberate characterization through to Tempus STA and Tempus ECO, enables designers to accurately analyze aging effects in the context of their design. This improved accuracy, in turn, allows for a re-examination of margins and subsequent PPA savings.

  2. Tempus Power Integrity Solution with Voltus Solution for STA-Aware IR Drop

    Traditional IR drop methodologies have struggled to keep up with the latest silicon technologies, leading to an increase in silicon failures at 7nm and below. The Tempus Power Integrity Solution integrates the Tempus and Voltus solutions to deliver next-generation IR drop analysis and fixing technology.

    Tempus Power Integrity identifies voltage-sensitive paths in your design and then automatically generates activity vectors that will activate these voltage-sensitive paths as well as nearby voltage aggressor cells, thereby finding potential IR drop failures that traditional methodologies miss. Once detected, the Tempus ECO Option will automatically fix IR drop issues by optimizing both the victim and aggressor paths.

  3. Timing Robustness

    Timing robustness is the statistical measure of chip performance. It co-exists with conventional signoff slack analysis and provides a complimentary metric to slack analysis for use during Tempus ECO optimization. Its key benefit is to ensure high reliability while avoiding unnecessary over-design and delivering improved PPA.

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Breakthrough Aging-Aware STA
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Blu Wireless Accelerates 5G mmWave Design Tapeout

Learn how Blu Wireless used the Tempus Solution to overcome design challenges and meet aggressive tapeout schedule

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Cadence Tempus Update Promises to Transform Timing Signoff User Experience

Shortening time to market with best-in-class PPA

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SiFive Tapeout FinFET Products Using Tempus ECO and Signoff

Discover how SiFive used Cadence tools to achieve better PPA and faster design closure time

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Customers Tape Out Using Tempus ECO and Signoff with Working Silicon
READ ARTICLE
  • Related Links

    • Mixed-Signal Implementation
    • Digital Advanced Node
    • Tempus Delivering Faster Timing Signoff with Optimal PPA
    • Inphi Reduces Time to Market with 2X Turnaround Time Reduction
    • Cadence Defines a New Signoff Paradigm with Tempus PI
    • Barefoot Networks Accelerates Timing Closure with Cloudburst Platform and Tempus Timing Signoff
  • Related Products

    • Quantus Extraction Solution
    • Voltus IC Power Integrity Solution
    • Innovus Implementation System
    • Voltus-Fi Custom Power Integrity Solution
    • Virtuoso Layout Suite

Resources

white paper

Intelligently Managing 3D-IC Timing Signoff

White Paper

Hierarchical Timing Analysis: Pros, Cons, and a New Approach White Paper

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Datasheet

Tempus Timing Signoff Solution

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Video

Signoff STA for Multi-Chiplet Design

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Videos

Tempus Power Integrity “True Signoff”

Maxlinear Signing-Off using Tempus with Confidence for FinFET Designs

Managing Signoff Corners with MMMC Flows

Mixed Signal STA Webinar

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

Tempus Timing Signoff Solution Delivers 2X Faster Time-to-Signoff Closure

News ReleasesVIEW ALL
  • Cadence Digital and Custom/Analog Design Flows Certified by TSMC for Latest N3E and N4P Processes 06/13/2022

  • Cadence 数字全流程获得 GlobalFoundries® 12LP/12LP+ 工艺平台认证 05/19/2022

  • Cadence 与TSMC和Microsoft扩大合作,以加速云端千兆级设计的时序签核 12/01/2021

  • Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack 11/17/2021

  • Samsung Foundry 选择全新 Tempus SPICE 级精度老化分析用于高可靠性应用 11/16/2021

Blogs VIEW ALL
Customers

The Tempus Timing Signoff Solution has been our timing tool for all of our SoCs that enable smart TV, set-top boxes and media connectivity. Its runtime performance, coupled with integration within the Cadence Innovus™ Implementation System, has allowed us to significantly reduce the time we spend in timing signoff.

Jacques Martinella, Vice President, Engineering, Sigma Designs

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The size and complexity characteristics of our latest design required a timing solution that could handle more than 50M cells quickly and efficiently. We determined that the Tempus Timing Signoff Solution was the right timing platform to address our signoff analysis and closure needs.

Toru Hiyama, General Manager for Platform Advanced Engineering Operation, Information and Telecommunication System Company, Hitachi, Ltd.

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The Tempus Timing Signoff Solution has enabled us to complete several successful tapeouts of our datacenter interconnect solutions. We were able to effectively use the tool for distributed multi-mode, multi-corner (MMMC) timing analysis and closure to get our products out the door and into the fab.

Lawrence Tse, Vice President of Engineering, Inphi

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Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview

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Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview

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