Tempus Timing Signoff Solution

The Cadence^® Tempus™ Timing Signoff Solution is the industry’s most trusted static timing analysis (STA) tool for FinFET designs. It is the fastest STA tool in the industry with unique distributed processing and cloud capabilities scaling to hundreds of CPUs to quickly complete even the largest designs.

With full foundry certification and a comprehensive set of advanced capabilities, the cloud-ready Tempus solution delivers SPICE-accurate results to hundreds of customers across a broad range of design types, from the high-performance designs to high-volume mobile designs, and mixed-signal chips on mature processes.

More than just an analysis tool, the Tempus solution is also deeply integrated with the Cadence Innovus™ Implementation System, Quantus™ Extraction Solution, and Voltus™ IC Power Solution.

Design Robustness

Cadence is focused on innovating in partnership with the industry’s most advanced companies to create even-greater design advantage and shorten time to market with best-in-class power, performance, and area (PPA).

One key aspect of interest to our customers is design robustness and its tradeoff with PPA. Design robustness is a six-prong approach to providing the highest quality of designs via Cadence’s suite of analysis tools—namely ultra-low Vdd robustness, aging robustness (aging-aware STA),voltage robustness (Tempus Power Integrity solution), process robustness (timing robustness), VT robustness, and interconnect robustness.

1. Aging-Aware STA with Liberate Characterization Solution

   High-reliability semiconductor applications such as automotive and defense must operate predictably over long timespans. To ensure high reliability, designers require accurate analysis of device performance over time without relying on pessimistic margining techniques that negatively impact PPA. To solve this problem, our unified flow, starting from Liberate characterization through to Tempus STA and Tempus ECO, enables designers to accurately analyze aging effects in the context of their design. This improved accuracy, in turn, allows for a re-examination of margins and subsequent PPA savings.

2. Tempus Power Integrity Solution with Voltus Solution for STA-Aware IR Drop

   Traditional IR drop methodologies have struggled to keep up with the latest silicon technologies, leading to an increase in silicon failures at 7nm and below. The Tempus Power Integrity Solution integrates the Tempus and Voltus solutions to deliver next-generation IR drop analysis and fixing technology.

   Tempus Power Integrity identifies voltage-sensitive paths in your design and then automatically generates activity vectors that will activate these voltage-sensitive paths as well as nearby voltage aggressor cells, thereby finding potential IR drop failures that traditional methodologies miss. Once detected, the Tempus ECO Option will automatically fix IR drop issues by optimizing both the victim and aggressor paths.

3. Timing Robustness

   Timing robustness is the statistical measure of chip performance. It co-exists with conventional signoff slack analysis and provides a complimentary metric to slack analysis for use during Tempus ECO optimization. Its key benefit is to ensure high reliability while avoiding unnecessary over-design and delivering improved PPA.