Cadence® QuickView Signoff Data Analysis Environment 是一个经过生产验证的全芯片高性能、高容量数据审查和独立芯片表面处理系统，支持多种设计格式、布局和制造数据。
QuickView Signoff Data Analysis Environment 是一个易于使用的高性能独立芯片表面处理系统，支持多种设计格式、布局和制造数据。QuickView Signoff Data Analysis Environment 可在几秒内加载大型布局（GDSII、OASIS®、LEF/DEF 和各种制造格式），提供一系列广泛的调试功能，包括网络连通性跟踪、可视化、叠层和 GDSII/OASIS® 编辑。
After full-chip verification, opening the database for chip finishing can take hours, and because there are several iterations at this stage, any productivity loss has a large impact.
Tatsuji Kagatani, Department Manager, Design Automation Department System Integration, Renesas Electronics Corporation
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