RF Spurs Impacting Your Performance? Not Anymore!
Quantus' Substrate Noise Analysis Functionality
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Key Benefits
- 数字和定制/模拟设计 3nm 客户应用的领导者
- 受到各个领先客户和晶圆代工厂的信任——为所有设计节点提供同类最优的精度，且设计收敛更快
- 5G 就绪，具备市场领先的功能，可支持所有 5G/RF 设计
- 支持大规模并行及云就绪，具有最快的单角和多角性能，并且可以为按时完成流片任务而线性扩展至成千个 CPU。
- 内置支持大规模并行且云就绪的 3D Field Solver 和 Quantus FS，可用于所有关键节点和高级节点的设计，以实现精确寄生
- 提供许多市场领先的分析特性和功能，以支持数字和晶体管设计提取
- 通过台积电 (TSMC) 晶圆代工厂认证，可用于 3nm 设计
- 在全球其他领先晶圆代工厂通过先进节点工艺认证
Cadence® Quantus™ Extraction Solution 是受业界信赖的签核寄生参数提取工具，是 3nm 设计应用和流片方面的领导者。Quantus 解决方案是一个统一的工具，在设计实现和签核中同时支持单元级和晶体管级提取。这是我们在 Innovus™ Implementation System 平台与 Virtuoso® 平台上提供的设计同步方法论中一个不可分割的组成部分。
Quantus Extraction Solution 是解决问题的关键，使设计人员在数字级和晶体管级工作流程上都能通过电阻 R 和电容 C 完成更多工作，从而确保按时流片。
Quantus 解决方案是数字和晶体管提取全流程的核心。
相关产品
Customers
After validating the runtimes of Cadence’s Quantus QRC Extraction Solution on benchmark designs, we have determined that it offers significant improvements without compromising signoff accuracy.
Sumbal Rafiq, Director of Engineering, AppliedMicro
Despite increasing SoC design sizes and interconnect process corners at advanced nodes, Open-Silicon has achieved design closure quickly by using the Quantus QRC Extraction Solution along with its best-in-class design methodologies and tools.
Radhakrishnan Pasirajan, Vice President of Silicon Engineering, Open-Silicon
Using these [Quantus, Tempus, and Tempus ECO] signoff engines, which are consistent with the Cadence Innovus Implementation System for both extraction and static timing analysis, ensured tight correlation and a reduction in design iterations during signoff for quick design convergence.
Dr. Paolo Miliozzi, VP of SoC Technology, MaxLinear
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