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Quantus' Substrate Noise Analysis Functionality
Cadence® Quantus™ Extraction Solution 是受业界信赖的签核寄生参数提取工具，是 3nm 设计应用和流片方面的领导者。Quantus 解决方案是一个统一的工具，在设计实现和签核中同时支持单元级和晶体管级提取。这是我们在 Innovus™ Implementation System 平台与 Virtuoso® 平台上提供的设计同步方法论中一个不可分割的组成部分。
Quantus Extraction Solution 是解决问题的关键，使设计人员在数字级和晶体管级工作流程上都能通过电阻 R 和电容 C 完成更多工作，从而确保按时流片。
After validating the runtimes of Cadence’s Quantus QRC Extraction Solution on benchmark designs, we have determined that it offers significant improvements without compromising signoff accuracy.
Sumbal Rafiq, Director of Engineering, AppliedMicro
Despite increasing SoC design sizes and interconnect process corners at advanced nodes, Open-Silicon has achieved design closure quickly by using the Quantus QRC Extraction Solution along with its best-in-class design methodologies and tools.
Radhakrishnan Pasirajan, Vice President of Silicon Engineering, Open-Silicon
Using these [Quantus, Tempus, and Tempus ECO] signoff engines, which are consistent with the Cadence Innovus Implementation System for both extraction and static timing analysis, ensured tight correlation and a reduction in design iterations during signoff for quick design convergence.
Dr. Paolo Miliozzi, VP of SoC Technology, MaxLinear
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