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Quantus Extraction Solution

Empowers designers to do "more" with highest levels of trust, integrity, and parasitic accuracy for on-time tapeout

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Key Benefits

 
  • Leader in 3nm customer adoptions for both digital and custom/analog designs 
  • Trusted by all leading customers and foundries—provides best-in-class accuracy for all design nodes for faster design convergence
  • 5G ready with market-leading functionality to support all 5G/RF designs
  • Massively parallel and cloud-ready for fastest single and multi-corner performance with linear scaling to 1000s of CPUs for on-time tapeout
  • Built-in massively parallel and cloud-ready 3D Field Solver, Quantus FS, for all critical and advanced-node designs for accurate parasitics
  • Provides many market-leading analysis features and functionality to support both digital and transistor designs extraction
  • Foundry certified at TSMC down to 3nm
  • Certified for advanced-node processes at other leading foundries worldwide
ASK US A QUESTION

 

The Cadence® Quantus™ Extraction Solution is the industry’s most trusted signoff parasitic extraction tool, and is a leader in 3nm design adoptions and tapeouts. As a single, unified tool, the Quantus solution supports both cell-level and transistor-level extractions during design implementation and signoff. It’s an integral component of our in-design methodology with both the Innovus™ Implementation System and Virtuoso® platforms. 

The Quantus Extraction Solution is the linchpin that allows designers to do more with Rs and Cs on both digital- and transistor-level flows, assuring on-time tapeout.

 

Quantus_Extraction_Solution_sm
The Quantus solution is central to full flow for both digital and transistor extraction

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Quantus FS—Massively Parallel and Cloud-Ready 3D Parasitic Extraction Field Solver

RF Spurs Impacting Your Performance? Not Anymore!

Quantus' Substrate Noise Analysis Functionality

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Related Products

  • Innovus Implementation System
  • Tempus Timing Signoff Solution
  • Voltus IC Power Integrity Solution
  • Voltus-Fi Custom Power Integrity Solution
  • Physical Verification System
  • Spectre AMS Designer
  • Virtuoso Analog Design Environment
  • Pegasus Verification System

Additional Resources

  • Quantus Field Solver Tech Brief
  • Field-Solver Parasitic Extraction Goes Mainstream
  • Integrated Virtual Dummy Metal Fill
  • Quantus FS Field Solver for the FinFET Era
  • Extraction Features for 7nm
  • Timing Signoff Tools Enables 400Gbps PAM4 SoC on 16FF Process
Videos

Whiteboard Wednesdays: Inductance Extraction for Digital Designs

Whiteboard Wednesdays - 3X Faster Design Closure with Quantus Integrated Virtual Metal Fill

Integrated Virtual Metal Fill - Don’t Emulate—Virtualize Metal Fill!

Inductance Extraction - Hold Time Failure, Ringing Effects, Reliability Failures!

Advanced Netlist Reduction - Up to 6X Reduction in Simulation Runtimes!

News ReleasesVIEW ALL
  • Cadence 数字全流程获得 GlobalFoundries® 12LP/12LP+ 工艺平台认证 05/19/2022

  • Cadence 数字和定制/模拟流程获TSMC最新 N3 和 N4 工艺认证 10/21/2021

  • Cadence与联电协作开发22ULP与ULL 制程认证, 加速先进消费、5G 和汽车应用设计 07/12/2021

  • Cadence 携手TSMC合作加速基于N3和N4工艺的移动、人工智能和超大规模计算应用开发 05/27/2021

  • Cadence Collaboration with Arm Enables Customers to Successfully Tape out Next-Generation Arm Mobile Designs 05/25/2021

Blogs VIEW ALL
Customers

After validating the runtimes of Cadence’s Quantus QRC Extraction Solution on benchmark designs, we have determined that it offers significant improvements without compromising signoff accuracy.

Sumbal Rafiq, Director of Engineering, AppliedMicro

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Despite increasing SoC design sizes and interconnect process corners at advanced nodes, Open-Silicon has achieved design closure quickly by using the Quantus QRC Extraction Solution along with its best-in-class design methodologies and tools.

Radhakrishnan Pasirajan, Vice President of Silicon Engineering, Open-Silicon

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Using these [Quantus, Tempus, and Tempus ECO] signoff engines, which are consistent with the Cadence Innovus Implementation System for both extraction and static timing analysis, ensured tight correlation and a reduction in design iterations during signoff for quick design convergence.

Dr. Paolo Miliozzi, VP of SoC Technology, MaxLinear

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