Cadence Pattern Analysis

Cadence^® Pattern Analysis provides the most effective layout analysis and optimization solution to maximize manufacturability from cell to full-reticle layout. Based on production-proven pattern analysis technology, Cadence Pattern Analysis combines traditional pattern analysis based on layout clips and the Squish^™ technology to deliver 10-100X faster performance and larger capacity than traditional DRC-based solutions. With Cadence Pattern Analysis, design and manufacturing teams can automate design quality improvements and accelerate design finishing prior to manufacturing. 

Benefits

High performance

• Up to 10-100X faster than other solutions means minutes vs. hours, hours vs. days
• Faster deck development with intuitive coding style and high-productivity GUI integrated in QuickView Signoff Data Analysis Environment

Scalable

• Scales linearly with area
• Each additional pattern has only a small impact on runtime
• Scales up to 100,000s of patterns to search and optimize

High capacity

• From cell to full-reticle capacity
• Handles millions of optimizations
• Highly distributable

Production proven

• In use to screen incoming tapeouts at major foundries
• Allows urgent foundry production fixes
• Foundation of pattern database to gather, monitor, and mitigate yield detractors
• Allows design optimization to improve yield of incoming designs

Versatile applications

• Single-pass design optimization
  • Single-pass single-deck search and optimization
  • Searches exact and fuzzy patterns
  • Automatically replaces or modifies patterns
  • Pattern deck includes both search and optimization definition
  • Increases recommended rules usage and DFM scoring with automated layout optimization
  • Integrated in Innovus^™ Implementation System, Virtuoso^® Layout Suite and QuickView Signoff Data Analysis Environment
  • Provides urgent production fixes
  • Saves hours with automated DRC fixing
• Interactive layout analysis
  • Interactive pattern capture, editing, search, and optimization integrated in QuickView Signoff Data Analysis Environment
  • Allows quick deck development, update, and validation
• Pattern profiling and classification
  • Automatically and quickly measure layout dimensions to generate histograms and reports on pattern usage
  • Identifies most frequent patterns and outliers
  • Groups similar patterns
  • Generates profiling reports and histograms
• Yield detractor monitoring
  • Creation and maintenance of pattern database of yield detractors
  • Scores yield detractor patterns and analyzes their complexity
  • Groups similar yield detractors
  • Enables systematic pattern-based dispositioning of yield detractors
• Pattern generation/enumeration
  • Generates and varies patterns of interest within their context
  • Generates patterns for DRC deck validation
  • Tests key generation for process hotspot coverage
• Hierarchy injection
  • Creates hierarchical layout from flat layout or flattened layout
  • Recovers hierarchy from layout that has been flattened
  • Accelerates subsequent processing
  • Reduced database size