Home
  • 产品
  • 解决方案
  • 支持与培训
  • 公司
  • ZH CN
    • SELECT YOUR COUNTRY OR REGION

    • US - English
    • Japan - 日本語
    • Korea - 한국어
    • Taiwan - 繁體中文

尖端设计工具

  • 数字设计与签核
  • 定制 IC/模拟/ RF 设计
  • 系统设计与验证
  • IP
  • IC 封装设计与分析

创新系统设计

  • Multiphysics System Analysis
  • 嵌入式原型验证
  • PCB 设计与分析
  • Computational Fluid Dynamics

万物智能

  • AI / 机器学习
  • AI IP 产品

CADENCE云服务

VIEW ALL PRODUCTS

数字设计与签核

Cadence® 数字与签核解决方案, 提供快速的设计收敛和更出色的可预测性,助您实现功耗、性能和面积(PPA)目标。

PRODUCT CATEGORIES

  • 逻辑等效性检查
  • SoC Implementation and Floorplanning
  • 形式验证与功能 ECO
  • 低功耗验证
  • RTL 综合
  • 功耗分析
  • Constraints and CDC Signoff
  • 硅签核
  • 库表征
  • 可测性设计

FEATURED PRODUCTS

  • Cerebrus Intelligent Chip Explorer
  • Genus Synthesis Solution
  • Innovus Implementation System
  • Tempus Timing Signoff Solution
  • Pegasus Verification System
  • RESOURCES
  • Flows
  • Voltus IC Power Integrity Solution

定制 IC/模拟/ RF 设计

Cadence® 定制、模拟和射频设计解决方案可以实现模块级和混合信号仿真、布线和特征参数提取等诸多日常任务的自动化,助您节省大量时间。

PRODUCT CATEGORIES

  • 电路设计
  • 电路仿真
  • 版图设计
  • 版图验证
  • 特征库提取
  • RF / Microwave Solutions

FEATURED PRODUCTS

  • Spectre X Simulator
  • Spectre FX Simulator
  • Virtuoso Layout Suite
  • Virtuoso ADE Product Suite
  • Virtuoso Advanced Node
  • Voltus-XFi Custom Power Integrity Solution
  • RESOURCES
  • Flows

Verification

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

PRODUCT CATEGORIES

  • 调试纠错分析
  • Virtual Prototyping
  • Emulation and Prototyping
  • 形式化验证与静态验证
  • 验证规划与管理
  • 仿真
  • 软件驱动验证
  • 验证IP(VIP)
  • System-Level Verification IP

FEATURED PRODUCTS

  • vManager Verification Management
  • Xcelium Logic Simulation
  • Palladium Enterprise Emulation
  • Protium Enterprise Prototyping
  • System VIP
  • RESOURCES
  • Flows
  • Jasper C Apps
  • Helium Virtual and Hybrid Studio

IP

An open IP platform for you to customize your app-driven SoC design.

PRODUCT CATEGORIES

  • Denali Memory Interface and Storage IP
  • 112G/56G SerDes
  • PCIe and CXL
  • Tensilica Processor IP
  • Chiplet and D2D
  • Interface IP

RESOURCES

  • Discover PCIe

IC 封装设计与分析

提升先进封装、系统规划和多织构互操作性的效率和准确性,Cadence 封装实现工具可实现自动化和精准度。

PRODUCT CATEGORIES

  • IC 封装设计
  • IC封装设计流程
  • SI/PI 分析
  • SI/PI 分析点工具
  • 跨平台协同设计与分析

Multiphysics System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

PRODUCT CATEGORIES

  • Computational Fluid Dynamics
  • 电磁求解器
  • 射频/微波设计
  • Signal and Power Integrity
  • 热求解器

FEATURED PRODUCTS

  • Clarity 3D Solver
  • Clarity 3D Solver Cloud
  • Clarity 3D Transient Solver
  • Celsius Thermal Solver
  • Fidelity CFD
  • Sigrity Advanced SI
  • Celsius Advanced PTI
  • RESOURCES
  • System Analysis Center
  • System Analysis Resources Hub
  • AWR Free Trial

嵌入式原型验证

PCB 设计与分析

Cadence® PCB 设计解决方案更好地结合了组件设计和约束驱动流程的系统级仿真,实现更短、更加可预测的设计周期。

PRODUCT CATEGORIES

  • 原理图设计
  • PCB Layout
  • 库与设计数据管理
  • 模拟/混合信号仿真
  • SI/PI Analysis
  • SI/PI 分析点工具
  • 射频/微波设计
  • Augmented Reality Lab Tools

FEATURED PRODUCTS

  • Allegro Package Designer Plus
  • Allegro PCB Designer
  • RESOURCES
  • What's New in Allegro
  • Advanced PCB Design & Analysis Blog
  • Flows

Computational Fluid Dynamics

AI / 机器学习

AI IP 产品

产业方案

  • 5G系统与子系统
  • 航天与国防
  • 汽车电子解决方案
  • Hyperscale Computing

技术方案

  • 3D-IC设计
  • 数字先进节点
  • AI / 机器学习
  • Arm-Based解决方案
  • Cloud 解决方案
  • Computational Fluid Dynamics
  • Functional Safety
  • 低功耗设计
  • 混合信号设计
  • 光电设计
  • 射频/微波
Designed with Cadence See how our customers create innovative products with Cadence

技术支持

  • 技术支持流程
  • 线上技术支持
  • 软件下载
  • 计算平台支持
  • 售后支持联络
  • 技术论坛

培训

  • 定制IC/模拟/设计
  • 设计语言及方法学
  • 数字设计与签核
  • IC封装
  • PCB设计
  • 系统设计与验证
  • Tensilica处理器IP
Link for support software downloads Stay up to date with the latest software
24/7 - Cadence Online Support Visit Now

公司介绍

  • 关于我们
  • 成功合作
  • 投资者关系
  • 管理团队
  • Computational Software
  • Alliances
  • 公司社会责任
  • Cadence大学计划
  • Intelligent System Design

企业文化与职业

  • Cadence文化与多样性
  • 招贤纳士

媒体中心

  • 会议活动
  • 新闻中心
  • 博客
Cadence Giving Foundation
Browse Cadence’s latest on-demand sessions and upcoming events. Explore More
ZH - China
  • US - English
  • Japan - 日本語
  • Korea - 한국어
  • Taiwan - 繁體中文
  • 产品
    • 尖端设计工具
      • 数字设计与签核
        • PRODUCT CATEGORIES
          • 逻辑等效性检查
          • SoC Implementation and Floorplanning
          • 形式验证与功能 ECO
          • 低功耗验证
          • RTL 综合
          • 功耗分析
          • Constraints and CDC Signoff
          • 硅签核
          • 库表征
          • 可测性设计
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 定制 IC/模拟/ RF 设计
        • PRODUCT CATEGORIES
          • 电路设计
          • 电路仿真
          • 版图设计
          • 版图验证
          • 特征库提取
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • 调试纠错分析
          • Virtual Prototyping
          • Emulation and Prototyping
          • 形式化验证与静态验证
          • 验证规划与管理
          • 仿真
          • 软件驱动验证
          • 验证IP(VIP)
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC 封装设计与分析
        • PRODUCT CATEGORIES
          • IC 封装设计
          • IC封装设计流程
          • SI/PI 分析
          • SI/PI 分析点工具
          • 跨平台协同设计与分析
    • 创新系统设计
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • 电磁求解器
          • 射频/微波设计
          • Signal and Power Integrity
          • 热求解器
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式原型验证
      • PCB 设计与分析
        • PRODUCT CATEGORIES
          • 原理图设计
          • PCB Layout
          • 库与设计数据管理
          • 模拟/混合信号仿真
          • SI/PI Analysis
          • SI/PI 分析点工具
          • 射频/微波设计
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Blog
          • Flows
      • Computational Fluid Dynamics
    • 万物智能
      • AI / 机器学习
      • AI IP 产品
    • CADENCE云服务
    • VIEW ALL PRODUCTS
  • 解决方案
      • 产业方案
        • 5G系统与子系统
        • 航天与国防
        • 汽车电子解决方案
        • Hyperscale Computing
      • 技术方案
        • 3D-IC设计
        • 数字先进节点
        • AI / 机器学习
        • Arm-Based解决方案
        • Cloud 解决方案
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗设计
        • 混合信号设计
        • 光电设计
        • 射频/微波
      • 产业方案
        • 5G系统与子系统
        • 航天与国防
        • 汽车电子解决方案
        • Hyperscale Computing
      • 技术方案
        • 3D-IC设计
        • 数字先进节点
        • AI / 机器学习
        • Arm-Based解决方案
        • Cloud 解决方案
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗设计
        • 混合信号设计
        • 光电设计
        • 射频/微波
      • 产业方案
        • 5G系统与子系统
        • 航天与国防
        • 汽车电子解决方案
        • Hyperscale Computing
      • 技术方案
        • 3D-IC设计
        • 数字先进节点
        • AI / 机器学习
        • Arm-Based解决方案
        • Cloud 解决方案
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗设计
        • 混合信号设计
        • 光电设计
        • 射频/微波
  • 支持与培训
      • 技术支持
        • 技术支持流程
        • 线上技术支持
        • 软件下载
        • 计算平台支持
        • 售后支持联络
        • 技术论坛
      • 培训
        • 定制IC/模拟/设计
        • 设计语言及方法学
        • 数字设计与签核
        • IC封装
        • PCB设计
        • 系统设计与验证
        • Tensilica处理器IP
      • 技术支持
        • 技术支持流程
        • 线上技术支持
        • 软件下载
        • 计算平台支持
        • 售后支持联络
        • 技术论坛
      • 培训
        • 定制IC/模拟/设计
        • 设计语言及方法学
        • 数字设计与签核
        • IC封装
        • PCB设计
        • 系统设计与验证
        • Tensilica处理器IP
      • 技术支持
        • 技术支持流程
        • 线上技术支持
        • 软件下载
        • 计算平台支持
        • 售后支持联络
        • 技术论坛
      • 培训
        • 定制IC/模拟/设计
        • 设计语言及方法学
        • 数字设计与签核
        • IC封装
        • PCB设计
        • 系统设计与验证
        • Tensilica处理器IP
  • 公司
      • 公司介绍
        • 关于我们
        • 成功合作
        • 投资者关系
        • 管理团队
        • Computational Software
        • Alliances
        • 公司社会责任
        • Cadence大学计划
        • Intelligent System Design
      • 企业文化与职业
        • Cadence文化与多样性
        • 招贤纳士
      • 媒体中心
        • 会议活动
        • 新闻中心
        • 博客
      • 公司介绍
        • 关于我们
        • 成功合作
        • 投资者关系
        • 管理团队
        • Computational Software
        • Alliances
        • 公司社会责任
        • Cadence大学计划
        • Intelligent System Design
      • 企业文化与职业
        • Cadence文化与多样性
        • 招贤纳士
      • 媒体中心
        • 会议活动
        • 新闻中心
        • 博客
      • 公司介绍
        • 关于我们
        • 成功合作
        • 投资者关系
        • 管理团队
        • Computational Software
        • Alliances
        • 公司社会责任
        • Cadence大学计划
        • Intelligent System Design
      • 企业文化与职业
        • Cadence文化与多样性
        • 招贤纳士
      • 媒体中心
        • 会议活动
        • 新闻中心
        • 博客

Pegasus CMP Predictor

Predict and reduce systematic and parametric variability at chip- and wafer-level due to CMP-induced topography and layer thickness variations

  • Overview
  • News and Blogs
  • Customers
  • Support and Training

Key Benefits

  • Accurately predicts multi-layer thickness and topography variability for the entire layer stack using a model-based approach developed using Pegasus CMP Calibrator and Process Optimizer (Pegasus CCPO)
  • Detects hotspots that affect yield and produces fixing guidelines during implementation through integration with Virtuoso Layout Suite and Innovus Implementation System at block, chip, and wafer level
  • Interfaces with Quantus Extraction Solution to identify timing-related problems and potentially reduce process guardbands
  • Enables CMP teams to detect CMP hotspots on incoming designs, optimize CMP manufacturing parameters, and improve overall wafer-scale systematic and parametric variations

The Cadence® Pegasus™ CMP Predictor predicts chemical and mechanical polishing (CMP) variations and their potential impact on your design for the entire layer stack. It turns the uncertainty of manufacturing process variation into predictable impacts and then minimizes these impacts during dummy fill definition and at the design stage to greatly enhance overall design performance and yield. Traditionally used at the chip level, Pegasus CMP is also applicable at the IP level with its unique block-based methodology and at the wafer level with advanced wafer-scale modeling and prediction. Pegasus CMP provides wafer-scale, full-chip, multi-level thickness and topography predictions for the entire stack, covering FEOL, MOL, and BEOL deposition, etch, and planarization processes.

CMP-related hotspots, such as copper pooling, can have detrimental effects on wafer and chip yield. The conventional rules-based approach to hotspot detection fails to capture long-range and multi-level CMP effects. Pegasus CMP uses a highly accurate model-based approach to find potential hotspot areas. It also feeds the thickness and topography variation data into extraction tools, enabling better RC and timing analysis. The Pegasus CMP thickness and topography variation output is also used to compare different dummy fill strategies and to optimize dummy fill approaches.

ASK US A QUESTION

 

Pegasus CMP integrates with the Cadence Virtuoso® Layout Suite and Cadence Innovus™ Implementation System, and interfaces closely with the Cadence Quantus™ Extraction Solution for a complete silicon signoff solution.

Image of CMP Predictor and various graphs
CMP Predictor

Pegasus CCPO is used by CMP, process, DFM, or PDK teams to develop CMP models used by Pegasus CMP. The model calibration is done from silicon thickness measurements and creates semi-physical models that accurately model silicon trends and topography variations. Pegasus CCPO has dedicated versions and modeling capabilities for deposition, etch, and planarization processes in FEOL, MOL, and BEOL. Pegasus CCPO supports many advanced CMP process features such as reverse etch back and deposition angle, as well as specialized process flows such as those used in CMOS image sensors, 3D NAND, copper-to-copper packaging, or other 3D-IC manufacturing. It now also includes wafer-level calibration and prediction capabilities.

With prediction and optimization capabilities at chip and wafer-level, Pegasus CCPO is used by CMP process and product teams to detect potential hotspots or yield limiting issues in new products coming to the manufacturing line, and to optimize the CMP process parameters for a specific product layout. Pegasus CCPO improves the CMP efficiency and yield for each product at the chip or wafer level.

cmp-process-optimizer
Pegasus CMP Calibration and Process Optimization Viewer


file
Pegasus CMP Calibration and Process Optimization Wafer-Level Prediction

Contact Us

TRAINING COURSES

Improve Manufacturability with CMP-Friendly Design​​
LOG IN TO VIEW PRESENTATION

SMIC describes the joint effort of SMIC with Cadence in creating DFM-clean libraries and accurate IP, CMP, and litho models for their worldwide customer base.

  • Related Products

    • Pegasus Computational Pattern Analytics
    • Pegasus Critical Area Analyzer
    • Pegasus Layout Pattern Analyzer
    • Process Proximity Compensation
News ReleasesVIEW ALL
  • Cadence与Samsung Foundry合作加速4纳米及更高工艺的超大规模计算SoC设计 04/08/2021

  • Cadence推出基于Samsung Foundry 14LPU工艺的汽车电子参考设计流程 04/08/2021

  • Cadence Collaborates with Arm and Samsung Foundry on Delivery of 5LPE Flow for Mission-Critical Applications Using Next-Generation “Hercules” CPU 10/08/2019

  • Cadence Digital Full Flow Achieves Certification for Samsung Foundry 5LPE Process Technology 07/02/2019

  • Cadence CMP Process Optimizer Enables Toshiba Memory Corporation to Accelerate Delivery of Advanced 3D Flash Memory Devices 02/25/2019

Blogs VIEW ALL
Customers

The Cadence massively parallel architecture allowed us to significantly reduce the time spent in signoff analysis, implementation, and closure so we could quickly deliver a quality reference design to market.

Shih Chin Lin, Senior Division Director, IP Development and Design Support Division, UMC

Read More or View All Customers

Working together with Cadence, we’re driving advances in CMP process performance.

Derek Witty, Vice President and General Manager, CMP Products Group, Applied Materials

Read More or View All Customers

After an extensive evaluation of all vendors in the market, we selected the complete Cadence DFM set of technologies for our most advanced ASIC and SoC designs.

Hiroshi Ikeda, Director of the System LSI Technology and Design Platform Development Department, Fujitsu Semiconductor Limited

Read More or View All Customers

Support

Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview

Cadence Online Support

  • Details about online support Learn more

  • Have an account already?Log in

  • New to support?Sign up

  • Online support overview Link to video

Customer Support

  • Support Process

  • Software Downloads

  • Computing Platform Support

  • University Software Program

  • Customer Support Contacts

Training

Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview

Course Delivery Methods

  • Instructor-Led Training
  • Online Training
  • Get Cadence Certified

Regional Training Information

  • China
  • Europe, Middle East, and Africa
  • India
  • Japan
  • Korea
  • North America
  • Singapore
  • Taiwan
Fortune 100 Best Companies to Work for 2022

A Great Place to Do Great Work!

Eighth year on the FORTUNE 100 list

Our Culture Join The Team

关注Cadence官方微信

We Chat QR Code
  • 产品
  • 定制 IC /模拟/ RF 设计
  • 数字设计与Signoff
  • IC 封装设计与分析
  • IP
  • PCB 设计与分析
  • 系统分析
  • 系统设计与验证
  • 所有产品
  • 公司
  • 关于我们
  • 管理团队
  • 投资者关系
  • 产业联盟
  • 就业机会
  • Cadence 学术网
  • Supplier
  • 媒体中心
  • Events
  • 新闻中心
  • Cadence 设计
  • 博客
  • 论坛
  • Glossary
  • 联系我们
  • 普通咨询
  • 客户支持
  • 媒体中心
  • 全球办公室查找

关注Cadence官方微信

We Chat QR Code

关注Cadence官方微信

We Chat QR Code

Stay Connected

Please confirm to enroll for subscription!

Stay Connected

Thank you for subscribing. You will get an email to confirm your subscription.

© 2022 Cadence Design Systems, Inc. All Rights Reserved.

  • 沪ICP备2020028284号-1, 沪ICP备18027754号
  • Terms of Use
  • Privacy
  • US Trademarks