Cadence® CMP Predictor predicts the Chemical and Mechanical Polishing (CMP) variations and their potential impact on your design for the entire layer stack. It turns the uncertainty of manufacturing process variation into predictable impacts, and then minimizes these impacts during the design stage to greatly enhance overall design performance and yield, at the chip level and also at IP level with Cadence CMP Predictor unique block-based methodology. CMP Predictor provides full-chip, multi-level thickness and topography predictions for the entire stack, covering FEOL, MOL, and BEOL deposition, etch, and planarization processes.
CMP-related hotspots, such as copper pooling, can have detrimental effects on chip yield. The conventional rules-based approach to hotspot detection fails to capture long-range and multi-level CMP effects. CMP Predictor uses a highly accurate model-based approach to finding potential hotspot areas. It also feeds the thickness and topography variation data into extraction tools, enabling better RC and timing analysis.
Cadence CMP Predictor integrates with the Cadence Virtuoso® Layout Suite and Cadence Innovus™ Implementation System, and interfaces closely with the Cadence Quantus™ Extraction Solution for a complete silicon signoff solution.
CMP Process Optimizer is used by CMP process, DFM, or PDK teams to develop CMP models used by CMP predictor. The model calibration is done from silicon thickness measurements and creates semi-physical models that accurately model the silicon trends and topography variations. CMP Process Optimizer has dedicated versions and modeling capabilities for deposition, etch, and planarization processes in FEOL, MOL, and BEOL. CMP Process Optimizer supports many advanced CMP process features such as reverse etch back and deposition angle, as well as specialized process flows such as those used in CMOS image sensors, 3D NAND, copper-to-copper packaging, or other 3D-IC manufacturing.
CMP Process Optimizer is also used by CMP process and product teams to detect potential hotspots or yield limiting issues in new products coming to the manufacturing line, and to optimize the CMP process parameters for a specific product layout. CMP Process Optimizer improves the CMP efficiency and yield for each product.
The Cadence massively parallel architecture allowed us to significantly reduce the time spent in signoff analysis, implementation, and closure so we could quickly deliver a quality reference design to market.
Shih Chin Lin, Senior Division Director, IP Development and Design Support Division, UMC
Working together with Cadence, we’re driving advances in CMP process performance.
Derek Witty, Vice President and General Manager, CMP Products Group, Applied Materials
After an extensive evaluation of all vendors in the market, we selected the complete Cadence DFM set of technologies for our most advanced ASIC and SoC designs.
Hiroshi Ikeda, Director of the System LSI Technology and Design Platform Development Department, Fujitsu Semiconductor Limited
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview
