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        • PRODUCT CATEGORIES
          • 逻辑等效性检查
          • SoC Implementation and Floorplanning
          • 形式验证与功能 ECO
          • 低功耗验证
          • RTL 综合
          • 功耗分析
          • Constraints and CDC Signoff
          • 硅签核
          • 库表征
          • 可测性设计
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
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          • Voltus IC Power Integrity Solution
      • 定制 IC/模拟/ RF 设计
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          • Spectre X Simulator
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          • System-Level Verification IP
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          • Palladium Enterprise Emulation
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          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC 封装设计与分析
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Virtuoso Layout Suite EAD

Avoid multiple design iterations with real-time feedback

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Key Benefits

  • Performs real-time analysis and optimization with built-in interconnect parasitic extraction engine that instantly evaluates your layout as it is created
  • Enables you to set electrical constraints and observe, in real time, whether these constraints are being met
  • Alerts you to electromigration issues that are created as your layout is drawn
  • Minimizes respins and “over design” via partial layout resimulation of existing interconnect parasitics
  • Reduces circuit design cycle by up to 30 percent
  • Enables you to optimize chip performance and utilize less area

Featuring a unique in-design electrical verification capability, the Cadence® Virtuoso® Layout Suite for Electrically Aware Design (EAD) enhances design team productivity and circuit performance for custom ICs.

With Virtuoso Layout Suite EAD, you’ll have the technology and methodology to avoid multiple design iterations and “over design.” You’ll be able to monitor electrical issues while your layout is created, and to electrically analyze, simulate, and verify interconnect decisions in real time. As a result, you’ll be able to achieve electrically correct-by-construction layout. The solution’s unique in-design electrical verification capability lets you reduce your circuit design cycle by up to 30 percent and achieve better chip performance in less area.

With Virtuoso Layout Suite EAD, you can save days to weeks of design time. The solution extracts interconnect parasitics in real time and works with partial designs. Layout and circuit designers will be able to collaborate more efficiently with enhanced real-time visibility into electrical issues. Because the solution works seamlessly with other tools in the Virtuoso platform, you’ll be able to capture currents and voltages from simulations run in Virtuoso Analog Design Environment, and pass this electrical information into the layout environment.

Refer to Blog post: Virtuoso Electrically Aware Design (EAD)—A New Approach to Custom/Analog Layout

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Virtuoso Layout Suite EAD Editing

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Learn how to improve designs with a custom layout providing in-design, real-time interconnect parasitic extraction and analysis

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    • Virtuoso Layout Suite
    • Virtuoso Schematic Editor
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  • Cadence Integrity 3D-IC 平台支持TSMC 3DFabric 技术,推进多Chiplet设计 10/26/2021

  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology 10/17/2019

  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology 04/23/2019

  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation 10/01/2018

  • Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout 04/10/2018

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