- 在单个 Virtuoso 环境中提供多技术工艺和多 PDK 支持
- Edit-in-Concert 可以跨多个技术工艺和多 PDK 同步编辑系统级封装模块和集成电路版图
- 可与 Allegro Package Designer Plus SiP Layout Option 相互操作，简化从设计到制造的流程
The Edit-in-Concert™ technology in the Cadence® Virtuoso® RF Solution lets designers edit across layouts and view the changes immediately at the system level within the Virtuoso environment. It enables RFIC and SiP module engineers to edit their layout design in the context of all ICs on the module or other fabrics (chip, module, board), making sure connectivity between bumps or bond wires are always correct, manufacturable and accurate.
The bidirectional interoperability between the Virtuoso Layout Suite and the SiP Layout Option solution helps automate an otherwise manual and error-prone efforts using other solutions. This helps to simplify the SiP module physical verification flow for DRC and DFM checking, with layout versus schematic (LVS) and layout versus abstract (LVA) checking tasks needed to guarantee design readiness for manufacturing.
Module Layout with Edit-in-Concert️ Technology
Use Virtuoso RF Solution to implement a multi-chip module. Work in a schematic-driven and connectivity-driven flow by capturing the multi-chip-module (SiP) logic connectivity using Virtuoso Schematic Editor. Enable a co-design layout flow using Virtuoso Layout Suite and interoperability with SiP Layout Option.