Library Characterization Flow

Designing at nanometer process technologies—and especially at advanced nodes (28nm and below)—requires many additional library views in order to achieve high-quality silicon and avoid silicon re-spins due to inaccurate signoff analysis. To manage leakage power, it is common to have cells with low-, typical-, and high-threshold voltages (SVT, LVT, HVT, etc.), each with different power and performance characteristics.

For accurate modeling of instance-specific voltage variation or temperature gradients, it’s vital to characterize each library at multiple voltages and multiple temperatures, increasing the total number of library corners. For the most advanced processes, it is becoming common to offer alternative cell libraries that improve yield at the expense of area and performance. As a result, creating and maintaining all of these library views is becoming a major bottleneck in the design flow.

Cadence provides a library characterization flow centered on the Cadence^® Virtuoso^® Characterization Suite. The suite delivers the industry’s most complete and robust solutions for the characterization and validation of your foundation intellectual property (IP)—from standard cells, I/Os, and complex multi-bit cells to memories and mixed-signal blocks. Cadence’s patented Inside View technology delivers better correlation to silicon by improving library throughput and ensuring timing, power, noise, and statistical coverage of your IP.  The Virtuoso Characterization Suite also integrates with the Cadence Spectre^® Circuit Simulator, the industry-standard SPICE simulator, delivering even greater throughput with the accuracy required for advanced-node libraries.

• Read article on “Library "Safe Margins"—Are They Really Saving Your Design?”