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          • Discover PCIe
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Virtuoso Analog Design Environment

Advanced design simulation for fast and accurate verification

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Key Benefits

  • Reduced learning curve with a simulator-independent environment
  • Maximum efficiency in the script-driven mode
  • Accelerated debug process using a variety of built-in analog analysis tools
  • Facilitated design correction via easy comparison of pre- and post-parasitic extracted designs
  • Quick detection of circuit problems via a clear visualization cockpit
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements

Designed to help users create manufacturing-robust designs, the Cadence® Virtuoso® Analog Design Environment is the advanced design and simulation environment for the Virtuoso platform. It gives designers access to a new parasitic estimation and comparison flow and optimization algorithms that help to center designs better for yield improvement and advanced matching and sensitivity analyses. By supporting extensive exploration of multiple designs against their objective specifications, the Virtuoso Analog Design Environment sets the standard in fast and accurate design verification.

Automotive TCL1 Certified for ISO 26262

The industry’s first analog/mixed-signal design implementation and verification flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The flow brings transistor-level designs from creation and simulation through physical implementation and verification using the Virtuoso ADE Product Suite and the Spectre® Circuit Simulation Platform. The Virtuoso ADE Verifier provides design engineers with an integrated means to validate the safety specifications against individual circuit specifications for design confidence. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

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  • Related Products

    • Virtuoso ADE Assembler
    • Virtuoso ADE Product Suite
    • Virtuoso ADE Explorer
    • Virtuoso ADE Verifier
    • Spectre Accelerated Parallel Simulator
    • Virtuoso Schematic Editor
Resource Library

Press Releases (13)

  • Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack | Cadence
  • Cadence 数字和定制/模拟流程获TSMC最新 N3 和 N4 工艺认证 | Cadence
  • Tower Semiconductor与Cadence 宣布,共同推出面向先进 5G 通信和汽车芯片开发全新参考流程 | Cadence
  • Cadence 携手TSMC合作加速基于N3和N4工艺的移动、人工智能和超大规模计算应用开发 | Cadence
  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology | Cadence
  • Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout | Cadence
  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process | Cadence
  • Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology | Cadence
  • Cadence Unveils Next-Generation Virtuoso Platform Featuring Advanced Analog Verification Technologies and 10X Performance Improvements Across Platform | Cadence
  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow | Cadence
  • Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs | Cadence
  • Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes | Cadence
  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry | Cadence

Datasheet (6)

  • Virtuoso ADE Explorer Datasheet
  • Virtuoso Variation Option Datasheet
  • Cadence® Virtuoso® ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions.
  • Virtuoso Analog Design Environment GXL Datasheet
  • Virtuoso Analog Design Environment XL Datasheet
  • Virtuoso Analog Design Environment L Datasheet

Webinar (2)

  • Addressing Smart Sensor Design Challenges for SoCs and IoT Webinar (IoT Webinar Series - Part 2)
  • Addressing Smart Sensor Design Challenges for SoCs and IoT (Part 1)

Customer Presentation (1)

  • 5nm Process Physical Implementation by Using Virtuoso-Innovus Flow with Mixed-Signal OpenAccess RapidPDK

Video (6)

  • 5nm Process Physical Implementation by Using Virtuoso-Innovus Flow with Mixed-Signal OpenAccess RapidPDK
  • Celebrating 25 Years of Virtuoso Innovation
  • Cadence In-Design DFM-LDE Adoption in ST SmartPower PDK
  • Addressing MCU Mixed-Signal Design Challenges for SoCs and IoT
  • Transistor-Level Reliability Analysis for Advanced Node
  • Verifying the RTL in an Analog Circuit

Customers Success (3)

  • Moving to UVM-MS to Meet Coverage Goals Case Study
  • Cadence and Melexis Success Story
  • Cadence and Fuji Electric Success Story

White Paper (2)

  • Save Time and Minimize Errors by Automating Co-Design and Co-Analysis of Chips, Boards, and Packages
  • Plan-Based Analog Verification Methodology White Paper

Success Story Video (1)

  • Transistor-Level Reliability Analysis for Advanced Node
VIEW ALL
News ReleasesVIEW ALL
  • Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack 11/17/2021

  • Cadence 数字和定制/模拟流程获TSMC最新 N3 和 N4 工艺认证 10/21/2021

  • Tower Semiconductor与Cadence 宣布,共同推出面向先进 5G 通信和汽车芯片开发全新参考流程 08/16/2021

  • Cadence 携手TSMC合作加速基于N3和N4工艺的移动、人工智能和超大规模计算应用开发 05/27/2021

  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology 10/17/2019

Blogs VIEW ALL
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