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    • 数字设计与Signoff
      数字设计与 Signoff 概述

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

      全流程数字解决方案 相关产品 A-Z

      工具目录
      • 逻辑等效性检查
        • Products
        • Conformal Equivalence Checker
        • Conformal Smart LEC
      • SoC Implemenation and Floorplanning
        • Products
        • Innovus Implementation System
        • First Encounter Design Exploration and Prototyping
        • Virtuoso Digital Implementation
      • 形式验证与功能 ECO
        • Products
        • Conformal ECO Designer
      • 低功耗验证
        • Products
        • Conformal Low Power
      • RTL 综合
        • Products
        • Stratus High-Level Synthesis
        • Genus Synthesis Solution
        • Joules RTL Power Solution
        • Virtuoso Digital Implementation
      • 功耗分析
        • Products
        • Joules RTL Power Solution
      • SDC and CDC Signoff
        • Products
        • Conformal Litmus
        • Conformal Constraint Designer
      • 硅签收
        • Products
        • Pegasus Verification System
        • Quantus Extraction Solution
        • Tempus Timing Signoff Solution
        • Assura Physical Verification
        • Physical Verification System
        • CMP Predictor
        • MaskCompose Reticle and Wafer Synthesis
        • QuickView Signoff Data Analysis
        • LDE Electrical Analyzer
        • Process Proximity
        • Pattern Analysis
        • Litho Physical Analyzer
        • Voltus IC Power Integrity Solution
        • Voltus-Fi Custom Power Integrity Solution
      • Library Characterization
        • Products
        • Liberate Trio Characterization Suite
        • Liberate MX Memory Characterization
        • Liberate AMS Mixed-Signal Characterization
        • Liberate LV Library Validation Solution
        • Liberate Characterization Solution
        • Liberate Variety Statistical Characterization
      • 可测性设计
        • Products
        • Modus DFT Software Solution
      • 流程
        • 流程
        • 3D-IC
        • 先进工艺节点
        • 基于 ARM 的设计
        • Library Characterization Flow
        • 低功耗
        • 混合信号
    • 定制 IC/模拟/ RF 设计
      定制 IC /模拟/ RF 设计概述

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

      概述 相关产品 A-Z

      工具目录
      • 电路设计
        • Tools
        • What's New in Virtuoso
        • Virtuoso Schematic Editor
        • Virtuoso ADE Product Suite
      • 电路仿真
        • Tools
        • Spectre Simulation Platform
        • Spectre X Simulator
        • Spectre eXtensive Partitioning Simulator
        • Spectre RF Option
        • Spectre AMS Designer
      • 版图设计
        • Tools
        • What's New in Virtuoso
        • Virtuoso Layout Suite
      • 版图验证
        • Tools
        • Virtuoso DFM
        • Physical Verification System
        • Virtuoso Integrated Physical Verification System
      • 特征库提取
        • Tools
        • Liberate Trio Characterization Suite
        • Virtuoso Liberate MX Memory Characterization Solution
        • Virtuoso Liberate AMS Mixed-Signal Characterization Solution
        • Liberate Variety Statistical Characterization
        • Liberate Characterization Solution
        • Liberate LV Library Validation Solution
      • 流程
        • 流程
        • 电学感知设计(EAD)
        • 先进工艺节点
        • Virtuoso RF Solution
        • Virtuoso System Design Platform
        • 5G Systems and Subsystems
    • 系统设计与验证
      系统设计与验证概述

      Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.

      系统验证套件 相关产品 A-Z

      工具目录
      • 调试纠错分析
        • Tools
        • Indago Debug Platform
        • Indago Debug Analyzer App
        • Indago Embedded Software Debug App
        • Indago Protocol Debug App
        • SimVision Debug
      • 硬件仿真加速器
        • Tools
        • Palladium Z1 Enterprise Emulation System
        • Palladium XP Series
        • Palladium Dynamic Power Analysis
        • Palladium Hybrid
        • SpeedBridge Adapters
        • Emulation Development Kit
        • Virtual JTAG Debug Interface
        • Accelerated VIP
        • QuickCycles Services
        • VirtualBridge Adapters
      • 形式化验证与静态验证
        • Tools
        • JasperGold Formal Verification Platform (Apps)
        • Assertion-Based Verification IP
      • FPGA 原型验证
        • Tools
        • Protium S1 Desktop Prototyping Platform
        • Protium X1 Enterprise Prototyping Platform
        • SpeedBridge Adapters
      • 验证规划与管理
        • Tools
        • vManager Metric-Driven Signoff Platform
      • 仿真与 Testbench 验证
        • Tools
        • Xcelium Parallel Simulator
        • Incisive Enterprise Simulator
        • Incisive Functional Safety Simulator
        • Incisive Specman Elite
      • 软件驱动验证
        • Tools
        • Perspec System Verifier
        • Indago Embedded Software Debug App
        • Virtual System Platform
      • 验证IP(VIP)
        • Tools
        • Accelerated Verification IP
        • Assertion-Based VIP
        • Verification IP (VIP) Catalog
      • 流程
        • 流程
        • 基于 ARM 设计的验证方案
        • 汽车功能安全性验证
        • 基于覆盖率度量的验证签收
        • 混合信号验证
        • 低功耗验证方法学
    • IP
      Cadence IP 主页

      这是一个开放的 IP 平台帮助您的APP驱动的 SoC 实现客户化设计

      了解更多

      工具目录
      • Interface IP
        • IP
        • PCI Express IP
        • CCIX IP
        • USB IP
        • SerDes IP
        • Ethernet IP
        • MIPI IP
        • HD Display IP
      • Denali Memory IP
        • IP
        • NAND Flash IP
        • DDR IP
        • HBM2 IP
        • SD / SDIO / eMMC IP
        • Octal and Quad SPI Flash Controller and PHY IP
      • Tensilica 处理器 IP
        • IP
        • HiFi DSPs for Audio, Voice, and Speech
        • ConnX DSPs for Radar, Lidar, and Communications
        • Vision DSPs for Imaging, Vision, and AI
        • Fusion DSPs for IoT
        • DNA Processor Family for On-Device AI
        • Tensilica Customizable Processors
        • Tensilica Reference Configuration
      • Analog IP
        • IP
        • Analog IP
      • System / Peripherals IP
        • IP
        • 8051 Microprocessor IP
        • System Bus Peripherals
        • Audio Controllers
      • 验证 IP
        • IP
        • Accelerated VIP
        • Assertion-Based VIP
        • Memory Models
        • Simulation VIP
        • Productivity Tools
        • Interconnect Solution
    • IC 封装设计与分析
      IC 封装设计与分析概述

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

      概述 相关产品 A-Z

      工具目录
      • IC 封装设计
        • Products
        • Allegro Package Designer
        • SiP Digital Architect
      • SI/PI 协同分析方案
        • Products
        • Allegro Sigrity SI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity Package Assessment and Extraction Option
        • Allegro Sigrity PI Base
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI 分析点工具
        • Products
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity Speed2000
        • Sigrity SystemSI
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity XtractIM
        • Sigrity XcitePI Extraction
      • 跨平台协同设计与分析
        • Products
        • OrbitIO Interconnect Designer
        • IO-SSO Analysis Suite
      • 流程
        • 流程
        • Cross-Substrate互连
        • IC/封装/PCB协同设计
        • InFO封装技术
        • Sigrity最新技术
        • Virtuoso System Design Platform
        • PDN设计
    • SYSTEM INNOVATION
    • 系统分析
      系统分析概述

      Cadence®系统分析解决方案提供高精度的电磁提取和仿真分析,确保您的系统在不同条件下正常运行。

      概述 相关产品 A-Z

      工具目录
      • Electromagnetic Solutions
        • Tools
        • Clarity 3D全波求解器
        • Sigrity XcitePI Extraction
        • Sigrity XtractIM
        • Sigrity PowerSI
      • Thermal Solutions
        • Tools
        • Celsius Thermal Solver
      • Flows
    • 嵌入式原型验证
    • PCB 设计与分析
      PCB 设计与分析概述

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

      概述 相关产品 A-Z 生态服务搜索

      工具目录
      • 原理图设计
        • Tools
        • Allegro Design Entry Capture/Capture CIS
        • Allegro Design Publisher
        • Allegro Design Authoring
        • Allegro FPGA System Planner
      • PCB 版图设计
        • Tools
        • Allegro PCB Designer
        • OrCAD PCB Designer
      • 库与设计数据管理
        • Tools
        • Allegro ECAD-MCAD Library Creator
        • Allegro EDM Solution
        • Allegro PCB Librarian
        • Allegro Pulse
      • 模拟/混合信号仿真
        • Tools
        • Allegro PSpice Simulator
        • OrCAD PSpice Designer
      • SI/PI 协同分析方案
        • Tools
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity SI Base
        • Allegro Sigrity PI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI 分析点工具
        • Tools
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity SystemSI
        • Sigrity Speed2000
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity PowerSI 3D EM Extraction Option
      • Allegro最新技术
        • Tools
        • Board Layout
        • Schematic Capture
        • Data Management
      • Sigrity最新技术
        • Tools
        • Sigrity 2018 Release
        • Sigrity Tech Tips
      • 流程
        • 流程
        • Multi-Board PCB System Design
        • 产品创建
        • ECAD MCAD 协同设计
        • Allegro Right First-Time Design
        • IO-SSO分析套件
        • 3D System Design Solutions
        • PDN设计
        • LPDDR4 完整分析方案
        • 功耗感知信号完整性分析
        • 接口感知方法
        • Sigrity串行链路分析
    • PERVASIVE INTELLIGENCE
    • Tensilica 处理器 IP
    • 机器学习
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    • INDUSTRIES
    • 5G Systems and Subsystems
    • 航天与国防
    • 汽车电子解决方案
    • TECHNOLOGIES
    • 3D-IC 设计
    • 先进工艺节点
    • Arm 解决方案
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    • 低功耗
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    • 光学
  • 技术服务
    • 技术服务概要

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    • 设计服务
    • 培训
    • 设计方法学服务
    • 虚拟集成化计算机辅助设计 (VCAD)
  • 支持与培训
    • 技术支持
      支持概要

      24小时全球范围的技术支持。

      了解更多 登录技术支持

      • 支持流程
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          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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        • 24/7 Support - Cadence Online Support

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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      • 客户支持联系人
        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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    • 全球培训课程目录
    • Custom IC / Analog / RF Design
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Circuit Design and Simulation
        • Featured Courses
        • Virtuoso ADE Assembler Series
        • Virtuoso ADE Verifier
        • Virtuoso Schematic Editor
        • Mixed Signal Simulations Using AMS Designer
        • Spectre Accelerated Parallel Simulator
        • Additional Courses
      • Electrically-Aware Design
        • Featured Courses
        • Physical Verification System
        • Virtuoso Analog Design Environment
        • Virtuoso Electrically-Aware Design with Layout-Dependent Effects
        • Virtuoso Schematic Editor
        • Quantus QRC Extraction Series
        • Spectre Accelerated Parallel Simulator
      • Infrastructure
        • Featured Courses
        • SKILL Development of Parameterized Cells
        • SKILL Language Programming
        • SKILL Language Programming Introduction
        • SKILL Programming for IC Layout Design
      • Layout Design and Verification
        • Featured Courses
        • Virtuoso Layout Pro Series
        • Virtuoso Space-Based Router
        • Virtuoso Floorplanner
        • Quantus QRC Extraction Series
        • Using Virtuoso Constraints Effectively
        • Virtuoso Connectivity-Driven Layout Transition
        • Physical Verification System
      • Library Characterization
        • Featured Courses
        • Cadence Library Characterization and Validation
        • Spectre Accelerated Parallel Simulator
        • Virtuoso ADE Assembler Series
      • Modeling
        • Featured Courses
        • Analog Modeling with Verilog-A
        • Behavioral Modeling with VHDL-AMS
        • Behavioral Modeling with Verilog-AMS
        • Mixed Signal Simulations Using AMS Designer
        • Real Modeling with SystemVerilog
        • Real Modeling with Verilog-AMS
        • Mixed-Signal IP and Testbench Reuse
      • RF Design
        • Featured Courses
        • Quantus QRC Transistor-Level T1: Overview and Technology Setup
        • Quantus QRC Transistor-Level T2: Parasitic Extraction
        • Quantus QRC Transistor-Level T3: Extracted View Flows and Advanced Features
        • Spectre Accelerated Parallel Simulator
      • Variation Aware Design
        • Featured Courses
        • Virtuoso ADE Assembler S1: Introducing the Assembler Environment
        • Virtuoso ADE Assembler S3: Circuit Checks, Device Asserts, and Reliability Analysis
        • Variation Analysis Using the Virtuoso ADE Assembler
        • Virtuoso Spectre Pro Series
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • Languages and Methodologies
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Assertions
        • Featured Courses
        • Verification with PSL
      • Behavioral Language for AMS Simulation
        • Featured Courses
        • Behavioral Modeling with VHDL-AMS
        • Behavioral Modeling with Verilog-AMS
        • Real Modeling with SystemVerilog
        • Real Modeling with Verilog-AMS
      • Scripting
        • Featured Courses
        • Perl for EDA Engineering
        • Tcl Scripting for EDA
      • Specman and UVMe
        • Featured Courses
        • Specman Advanced Training
        • Specman Fundamentals for Block-Level Environment Developers
      • SystemC
        • Featured Courses
        • C++ Language Fundamentals for Design and Verification
        • SystemC Language Fundamentals
        • SystemC Transaction-Level Modeling (TLM 2.0)
      • SystemVerilog and UVM
        • Featured Courses
        • Real Modeling with SystemVerilog
        • SystemVerilog Advanced Register Verification Using UVM
        • SystemVerilog for Design and Verification
        • SystemVerilog for Verification
      • Verilog and VHDL
        • Featured Courses
        • VHDL Language and Application
        • Verification with PSL
        • Verilog for VHDL Users
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Digital Design and Signoff
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Block and Hierarchical Implementation
        • Featured Courses
        • Analog-on-Top Mixed-Signal Implementation
        • Innovus Implementation System (Block)
        • Innovus Implementation System (Hierarchical)
      • Equivalence Checking
        • Featured Courses
        • Encounter Conformal ECO
        • Logic Equivalence Checking with Conformal EC
      • Silicon Signoff
        • Featured Courses
        • Voltus Power-Grid Analysis and Signoff
      • Synthesis
        • Featured Courses
        • Advanced Synthesis with Genus Stylus Common UI
        • Genus Synthesis Solution with Stylus Common UI
        • Low-Power Synthesis Flow with Genus Stylus CommonUI
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • IC Package Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Cross-Platform Co-Design and Analysis
        • Featured Courses
        • OrbitIO System Planner
        • SiP Layout
      • IC Package Design
        • Featured Courses
        • SiP Layout
      • SI/PI Analysis Integrated Solution
        • Featured Courses
        • Allegro Sigrity PI
        • Allegro Sigrity Package Assessment and Model Extraction
        • Allegro Sigrity SI Foundations
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • SI/PI Analysis Point Tools
        • Featured Courses
        • Allegro Sigrity Package Assessment and Model Extraction
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • PCB Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Analog/Mixed-Signal Simulation
        • Featured Courses
        • Allegro AMS Simulator Advanced Analysis
        • Analog Simulation with PSpice
      • Design Authoring
        • Featured Courses
        • Allegro Design Entry HDL Basics
        • Allegro Design Entry HDL SKILL Programming Language
        • Allegro Design Entry Using OrCAD Capture
        • Allegro System Architect
        • Allegro Team Design Authoring
      • Library and Design Data Management
        • Featured Courses
        • Allegro Design Workbench for Administrators
        • Allegro Design Workbench for Engineers and Designers
        • Allegro Design Workbench for Librarians
        • Allegro PCB Librarian
      • PCB Layout
        • Featured Courses
        • Allegro High-Speed Constraint Management
        • Allegro PCB Editor Basic Techniques
        • Allegro PCB Editor Intermediate Techniques
        • Allegro PCB Router Basics
      • SI/PI Analysis Integrated Solution
        • Featured Courses
        • Allegro Sigrity PI
        • Allegro Sigrity SI Foundations
        • Sigrity PowerSI for Model Generation and Analysis
        • Sigrity PowerDC and OptimizePI
      • SI/PI Analysis Point Tools
        • Featured Courses
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • System Design and Verification
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Emulation and Acceleration
        • Featured Courses
        • Protium Rapid Prototyping Platform
      • Formal Verification
        • Featured Courses
        • JasperGold Formal Fundamentals
        • Verification with PSL
      • Planning and Management
        • Featured Courses
        • Foundations of Metric Driven Verification
        • Metric Driven Verification using Incisive vManager
      • Scripting
        • Featured Courses
        • Perl for EDA Engineering
        • Tcl Scripting for EDA
      • Simulation, Testbench and Debug
        • Featured Courses
        • Xcelium Fault Simulator
        • Incisive Functional Safety Simulator
        • Low-Power Simulation with IEEE Std 1801 UPF
      • Specman and UVMe
        • Featured Courses
        • Specman Advanced Training
        • Specman Fundamentals for Block-Level Environment Developers
      • SystemC
        • Featured Courses
        • C++ Language Fundamentals for Design and Verification
        • SystemC Language Fundamentals
        • SystemC Transaction-Level Modeling (TLM 2.0)
      • SystemVerilog and UVM
        • Featured Courses
        • Real Modeling with SystemVerilog
        • SystemVerilog Advanced Register Verification Using UVM
        • SystemVerilog for Design and Verification
        • SystemVerilog for Verification
      • Verilog and VHDL
        • Featured Courses
        • VHDL Language and Application
        • Verification with PSL
        • Verilog for VHDL Users
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Tensilica Processor IP
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • ConnX DSPs
        • Featured Courses
        • Tensilica ConnX BBE16EP Baseband Engine
        • Tensilica ConnX BBE32EP Baseband Engine
        • Tensilica ConnX BBE64EP Baseband Engine
      • Fusion DSPs
        • Featured Courses
        • Tensilica Fusion F1 DSP
        • Tensilica Fusion G3 DSP
      • HiFi DSPs
        • Featured Courses
        • Tensilica HiFi 2/EP/Mini Audio Engine ISA
        • Tensilica HiFi 3 Audio Engine ISA
        • Tensilica Audio Codec API
      • Tensilica Processors
        • Featured Courses
        • Tensilica Processor Fundamentals
        • Tensilica Instruction Extension Language and Design
        • Tensilica Xtensa Hardware Verification and EDA
        • Tensilica Xtensa Processor Interfaces
      • Vision DSPs
        • Featured Courses
        • Tensilica Vision P5 DSP
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

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定制IC/模拟/RF设计

通过自动实现仿真、布线与特征单元库提取,节省设计开发时间

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  • Library Characterization

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  • Circuit Design

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  • Circuit Simulation

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  • RF Design

    • Virtuoso Schematic Editor
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    • Spectre RF Option
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理解“设计的相互依赖性对电路性能的影响”

打造智慧生活时代的电子系统时,未来的设计人员需要掌握半导体、芯片封装、系统互连、软硬件集成、系统验证等各个层面技术。传统设计方法孤立地处理以上各层面的问题,已无法满足日益增长的复杂性、低功耗要求和更紧迫的产品上市时间。通过与在电子设计自动化、知识产权、芯片制造以及价值链其他部分的产业生态领导者合作,为“系统设计实现”(System Design Enablement,SDE)营造完善的综合环境,成功的企业得以繁荣发展。Cadence® 定制 IC/模拟/RF解决方案是SDE战略的核心组成部分。

通过选择性地对定制IC的非关键组件进行自动化设计,工程师们可以将精力专注于打造更精准的设计。Cadence电路设计解决方案,包括Virtuoso®模拟设计环境、Spectre® 仿真解决方案和Liberaterate™ 特征库提取与验证解决方案,以及量身打造的电学感知设计(EAD)和先进工艺节点设计流程,使用户可以快速、准确地输入设计概念,并在电路图里自然流畅地管理设计内容。在能感知寄生效应的先进设计环境下,用户能够对一个模拟、RF或混合信号设计的许多相互依赖性进行抽象化和可视化,并理解与决定其对电路性能的影响。

Virtuoso Custom IC, Analog, and RF Design
Resource Library VIEW ALL

Video (85)

  • Virtuoso Design Platform for Next-Generation Custom IC and System Design
  • Toshiba Electronic Device Solutions Overcomes Complexities of Advanced-Node Designs
  • Meeting the Challenges of Chip Design Using the Virtuoso Suite
  • Advanced Characterization with Cadence Liberate Trio Characterization Suite
  • Lumerical and Cadence Partner to Address the State of Photonics
  • Virtuoso RF Solution Electromagnetic Analysis
  • Virtuoso RF Solution Edit-in-Concert™ Technology
  • Faster Circuit Simulation Trends for Analog Circuit Design
  • Balancing Accuracy, Performance, and Capacity for Large Analog Designs
  • Solving Analog Simulation Challenges in Complex Designs
  • GlobalFoundries Expert Insights: Aging Analysis for IoT and Automotive Applications
  • STMicroelectronics 20nm Constraint Driven Modgen Flow
  • Looking for Efficiency While Leveraging the MathWorks and Cadence Alliance
  • Smart EM Simulation Automates Work for RFIC and RF Module Designs
  • New Virtuoso Design Platform for Next-Generation Custom IC and System Design
  • NI AXIEM 3D Planar EM Analysis in the Virtuoso Environment
  • Overview of the Characterization Interface in Liberate Trio Characterization Suite
  • Achieve greater throughput and productivity with Liberate Trio Characterization Suite
  • Library Characterization in the Cloud
  • Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications
  • How to Meet the Quality, High Reliability, and Safety Requirements for Analog and Mixed-Signal ICs in Mission-Critical Applications
  • Easily Adopt Electro-thermal Simulation for Your High-Reliability Analog Designs
  • Improvements in Modeling Device Aging Analysis: Extending Product Lifetime
  • Analog Defect Simulation and Analysis for Complex Systems
  • Automotive System Trends and the Integration of Analog Electronic Dependability
  • Fast & Efficient Memory Verification and Characterization for Advanced On Chip Variation
  • Cadence Legato Memory Solution Verification Overview
  • Increase Your Productivity with Cadence Legato Memory Solution
  • Legato Memory Solution Characterization Overview
  • Virtuoso ADE Explorer, Assembler, and Verifier- hear what people are saying about training
  • STMicroelectronics – New flow for Analog Top Level Design
  • LG Electronics – New Methodology for Full-Chip RFIC Transceiver Co-Verification
  • Introducing New Integration with MathWorks
  • Extending the Power of MathWorks MATLAB Inside the Virtuoso ADE Suite
  • Combined MathWorks and Cadence Design Flow for Analog/Mixed-Signal IC Development
  • Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
  • Ultra-Low Voltage SRAM: Addressing the Characterization Challenge
  • PhoeniX Software: Developing First-Time-Right Photonic ICs
  • Omni Design: Increased Speed and Accuracy with Spectre XPS
  • STMicroelectronics - Improving Productivity with Virtuoso SPD
  • austriamicrosystems - Cadence Unified Custom/Analog Flow Success Video
  • ams Reduces IC Development Effort by Collaborating with Cadence on Layout Productivity
  • Closing Gaps in Mixed-Signal Power Implementation Using a Consistent Power Intent
  • Analog/MS Flow with EAD, Device Checker, and PVS PERC Features
  • Global Unichip: 20nm Testchip Tapeout with Cadence and TSMC
  • STMicroelectronics - Virtuoso Custom/Analog Expert Insights
  • Characterizing 22FDX Library at GLOBALFOUNDRIES
  • Cadence Pattern Matching and DFM Signoff
  • Silicon Labs Leverages Cadence Mixed-Signal Solution for Mixed Signal Simulation, Implementation and Signoff
  • Verifying Data Converters with SPICE Accuracy in Minutes and Hours
  • Developing ASICs for High-End ground and space apps at Saphyrion
  • Cadence Spectre XPS FastSPICE Simulator for 10X Faster Throughput
  • Verification Made Easy: Learn How to Avoid Mistakes with Virtuoso ADE Verifier
  • Celebrating 25 Years of Virtuoso Innovation
  • Easily Explore and Analyze Your Design with Virtuoso ADE Product Suite
  • The New Sound of Analog Design: Simplify Design Verification with Virtuoso ADE Product Suite
  • Faster Timing Characterization of Analog Macros
  • Fairchild Semiconductor Eases Floorplanning Challenges of Mixed-Signal Design with Virtuoso Platform
  • New Capabilities for Accelerating High-Speed Routing
  • Virtuoso Electrically Aware Design
  • Offering Leading Edge Total Solutions - GLOBALFOUNDRIES Design Ready 14nm Eco System
  • Virtuoso IPVS for Advanced Node Design
  • Advanced Node Multi-Patterning Technologies within Virtuoso Environment
  • Producing Analog/Mixed-Signal IP Requires a Best-in-Class Design Flow
  • Custom Layout Methodologies with Virtuoso Advanced Node
  • Cadence In-Design DFM-LDE Adoption in ST SmartPower PDK
  • Using VSR for Chip Routing on ST smARTpower Technologies
  • TowerJazz AMS Reference Flow
  • Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization
  • Place-and-Route in Under a Day for Allegro Microsystems
  • How Electrically Aware Design Reduces Iterations
  • Faster Mixed-Signal Simulation Ensures Chip Performance
  • Liberate MX Product Demonstration
  • Analog Devices Raises Productivity with ModGen Tools
  • Get Real-Time Electrical Feedback with Cadence Virtuoso Layout Suite for Electrically Aware Design
  • Spectre XPS Demonstration
  • Freescale Accelerates Layout Via Constraint-Driven Design Flow
  • Verifying PLLs with SPICE Accuracy in Minutes and Hours
  • Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM
  • Addressing MCU Mixed-Signal Design Challenges for SoCs and IoT
  • Verifying the RTL in an Analog Circuit
  • PMC Gains Faster Analog IP Verification with Virtuoso Platform
  • STMicroelectronics Automates Full Custom Analog Layout Flow Using Constraints
  • CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS
  • Transistor-Level Reliability Analysis for Advanced Node

Datasheet (38)

  • Virtuoso ADE Verifier Chinese Datasheet
  • Spectre X Simulator
  • Cadence PCell Designer Datasheet
  • Spectre Simulation Platform Datasheet
  • Spectre Extensive Partitioning Simulator (XPS) Datasheet
  • Spectre Accelerated Parallel Simulator (APS) Datasheet
  • Spectre X Simulator Datasheet
  • Liberate Characterization Portfolio Datasheet
  • Liberate Trio Characterization Suite Datasheet
  • Legato Reliability Solution Cadence
  • Quantus Extraction Solution
  • Legato Memory Solution
  • Virtuoso ADE Verifier Datasheet
  • Virtuoso Layout Suite GXL Datasheet
  • Virtuoso ADE Assembler Datasheet
  • Virtuoso ADE Explorer Datasheet
  • Virtuoso Variation Option Datasheet
  • Spectre RF Option Datasheet
  • Virtuoso Layout Suite L Datasheet
  • Allegro Package Designer Plus SiP Layout Option
  • Virtuoso Analog Design Environment Family
  • Virtuoso Schematic Editor L and XL Datasheet
  • Virtuoso Analog Design Environment GXL Datasheet
  • Virtuoso Chip Assembly Router Datasheet
  • Cadence Physical Verification System Datasheet
  • Virtuoso Variation-Aware Implementation Option Datasheet
  • Spectre AMS Designer Datasheet
  • Virtuoso Layout Suite for Electrically Aware Design Datasheet
  • Virtuoso Mixed-Signal Behavioral Modeling Technology Datasheet
  • Virtuoso Visualization and Analysis Datasheet
  • Virtuoso Analog Design Environment XL Datasheet
  • Virtuoso Digital Implementation Datasheet
  • Virtuoso DFM Datasheet
  • Virtuoso Analog Design Environment L Datasheet
  • Virtuoso Custom Design Platform XL Datasheet
  • Cadence SiP RF Design Datasheet
  • Cadence Space-based Router Datasheet

Customers Success (10)

  • Altair and Cadence Success Story
  • Moving to UVM-MS to Meet Coverage Goals Case Study
  • Cadence and Texas Instruments Success Story
  • Cadence and Melexis Success Story
  • Cadence and Rohde & Schwarz Success Story
  • Cadence and Fuji Electric Success Story
  • Cadence and Teradyne Success Story
  • Cadence and Realtek Success Story
  • Cadence and Multigig Success Story
  • Cadence and Spansion Success Story

Press Releases (43)

  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications
  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation
  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology
  • Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation
  • Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies
  • Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy
  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology
  • Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design
  • Cadence Selected as Primary EDA Tool Vendor by GLOBALFOUNDRIES
  • Cadence Delivers Advanced Packaging Reference Flow for Samsung Foundry Customers
  • Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology
  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
  • Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations
  • Cadence Design Systems and NI Announce Collaboration to Simplify Next-Generation Semiconductor and RF Development
  • Cadence Debuts Industry’s First Analog IC Design-for-Reliability Solution
  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
  • Cadence Supports New TSMC WoW Advanced Packaging Technology
  • Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout
  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
  • Cadence Announces Legato Memory Solution, Industry’s First Integrated Memory Design and Verification Solution
  • New Cadence Virtuoso System Design Platform Provides Seamless Design Flow Between IC, Package and Board
  • Cadence and MathWorks Announce New Integration to Accelerate Data Mining and Analytics
  • Cadence and MathWorks Provide System-Level Simulation Solutions for Mixed-Signal IoT and Automotive Applications
  • Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
  • Cadence Unveils Next-Generation Virtuoso Platform Featuring Advanced Analog Verification Technologies and 10X Performance Improvements Across Platform
  • Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
  • Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process
  • Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs
  • Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
  • Cadence Digital, Custom/Analog and Signoff Tools Achieve TSMC Certification for 10nm FinFET Process
  • Cadence Implementation and Signoff Tools Certified on Intel Custom Foundry 14nm Process
  • Cadence Digital and Custom/Analog Tools Achieve TSMC Certification for 10nm FinFET Early Design Starts
  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry
  • Cadence Announces Virtuoso Liberate AMS, Industry's First Dynamic Simulation Characterization Solution for Mixed-Signal Designs
  • TSMC Adopts Cadence Solutions for 16nm FinFET Library Characterization
  • Cadence Virtuoso Layout Suite for Electrically Aware Design Adopted By ON Semiconductor
  • ARM Implements the Cadence Library Characterization Solution for Advanced Node Foundation IP Development
  • Cadence Significantly Accelerates Chip Design With New Virtuoso for Electrically Aware Design
  • Cadence Characterization Solution for Complex Multi-bit Cells Delivers Power and Performance Benefits for Yamaha
  • Cadence Introduces New Mixed-signal and Radio Frequency Capabilities to Address Wireless Design Challenges
  • Cadence Announces New OrCAD Technology to Help Shorten PCB Design Cycles

White Paper (15)

  • Compressing Datasets Created During Silicon Design White Paper
  • Revolution by Evolution: Getting to the Next Technology Breakthrough in Analog Simulation
  • Consolidating RF Flow for High-Frequency Product Design
  • Analog Reliability Analysis for Mission-Critical Applications White Paper
  • Improving Test Coverage and Eliminating Test Ecapes Using Analog Defect Analysis White Paper
  • Addressing Process Variation and Reducing Timing Pessimism at 16nm and Below White Paper
  • Addressing Memory Characterization Capacity and Throughput Requirements with Dynamic Partitioning White Paper
  • Save Time and Minimize Errors by Automating Co-Design and Co-Analysis of Chips, Boards, and Packages
  • Massively Parallel Electrically Aware Design White Paper
  • Plan-Based Analog Verification Methodology White Paper
  • Accelerating Monte Carlo Analysis at Advanced Nodes White Paper
  • Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment, Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment White Paper
  • A Faster, More Accurate Approach for System-Level Performance Verification of a Wireless RFIC Design White Paper
  • Taming the Challenges of 20nm Custom/Analog Design White Paper
  • Solutions for Mixed-Signal SoC Verification White Paper

Success Story Video (9)

  • Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
  • austriamicrosystems - Cadence Unified Custom/Analog Flow Success Video
  • Validating Design Intent and Improving Design Quality at Micron
  • Characterizing 22FDX Library at GLOBALFOUNDRIES
  • Silicon Labs Leverages Cadence Mixed-Signal Solution for Mixed Signal Simulation, Implementation and Signoff
  • Faster Timing Characterization of Analog Macros
  • Analog Devices Raises Productivity with ModGen Tools
  • Freescale Accelerates Layout Via Constraint-Driven Design Flow
  • Transistor-Level Reliability Analysis for Advanced Node
Videos

Celebrating 25 Years of Virtuoso Innovation

Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution

Characterizing 22FDX Library at GLOBALFOUNDRIES

Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM

Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization

Combined MathWorks and Cadence Design Flow for Analog/Mixed-Signal IC Development

Faster Timing Characterization of Analog Macros

TowerJazz AMS Reference Flow

The New Sound of Analog Design: Simplify Design Verification with Virtuoso ADE Product Suite

News ReleasesVIEW ALL
  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation 12/02/2019

  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology 10/17/2019

  • Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation 10/17/2019

  • Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies 09/25/2019

BlogsVIEW ALL
Customers

Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block.

Martin Kejhar, Senior Technical Staff Engineer and Scientist, ON Semiconductor

Read More or View All Customers

定制IC/模拟/RF设计 Products A-Z

L

  • Legato 可靠性解决方案
  • Liberate AMS Mixed-Signal Characterization
  • Liberate Characterization Solution
  • Liberate LV Library Validation Solution
  • Liberate MX Memory Characterization
  • Liberate Trio Characterization Suite
  • Liberate Variety Statistical Characterization

M

  • MathWorks and Cadence Solutions

S

  • Spectre Accelerated Parallel Simulator
  • Spectre AMS Designer
  • Spectre eXtensive Partitioning Simulator (XPS)
  • Spectre RF Option
  • Spectre Simulation Platform
  • Spectre X Simulator

V

  • Virtuoso ADE Assembler
  • Virtuoso ADE Explorer
  • Virtuoso ADE Product Suite
  • Virtuoso ADE Verifier
  • Virtuoso Analog Design Environment
  • Virtuoso DFM
  • Virtuoso Integrated Physical Verification System
  • Virtuoso Layout Suite
  • Virtuoso Layout Suite EAD
  • Virtuoso Liberate AMS Mixed-Signal Characterization Solution
  • Virtuoso Liberate Characterization Solution
  • Virtuoso Liberate LV Library Characterization Solution
  • Virtuoso Schematic Editor
  • Virtuoso Space-Based Router
  • Virtuoso Variety Statistical Characterization Solution
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