Overview
Shifting to Chiplet-Based SoC Designs
The semiconductor industry is undergoing a major transformation from traditional monolithic system-on-chip (SoC) architectures to modular, multi-die, and chiplet-based designs. This approach allows for more integrated and customizable silicon solutions that scale designs, optimize yields, and address rising fabrication costs. It optimizes production efficiency, increases cost efficiency, and improves design flexibility, making chiplets crucial for advanced semiconductor solutions across a wide range of applications.
Cadence IP solutions, EDA tools, advanced packaging technologies, and design services enable the disaggregation of monolithic SoC designs into modular chiplets. This comprehensive suite includes full implementation flows, die-to-die connectivity using UCIe™ standards, reusable verification IP, and multiphysics system analysis to accelerate time to market and reduce costs. These innovations offer designers greater flexibility and scalability, streamlining the development of multi-die and chiplet systems. Cadence’s dedicated Custom Silicon Design Services help customers de-risk designs and achieve power, performance, and area goals. Working with Cadence silicon engineering experts, designers can quickly turn concepts into packaged, tested parts, enabling them to realize their chiplet ambitions quicker and with fewer engineering resources.
Key Benefits
Realize Your Chiplet Ambitions
Cadence Chiplet Platform Solutions address the most pressing business and engineering challenges that customers have in designing their next-generation designs.
Cost Efficiency
Reduce device design time and cost by focusing on unique value-adds and leveraging partners for other product complexities
Customization
Modular, scalable, and customizable designs that enable large systems with multi-chip systems with scalable integration
Configurability
Enhanced portfolio management and product diversification for greater levels of integration and chiplet reuse in next-generation designs
Cadence Ecosystem
Proven and flexible engagement model. Standards-based, including interoperability across Arm Chiplet System Architecture (CSA), UCIe, and imec Automotive Chiplet Program (ACP). Built on the foundation of leadership EDA, IP development, and design services
Applications
Physical AI Systems: The Next Step in the AI Journey
Automotive
The automotive industry is on the brink of a major transformation, largely driven by advancements in autonomous vehicles and chiplet technologies to power those systems. This innovative approach to SoC design allows for the creation of cost-effective and powerful processing systems that are essential for next-generation autonomous vehicles. Automotive companies are now able to integrate more sophisticated AI-based inference solutions, which enhance vehicle intelligence and improve safety features while optimizing power consumption. By employing chiplet technology, designers can quickly iterate on designs, scale systems up and down their product lineup, and accelerate the deployment of smarter and safer vehicle systems.
Robotics
Robotics is set to experience a groundbreaking evolution with the adoption of chiplet technology, which promises to deliver unprecedented levels of performance and design flexibility. The ability to design more complex AI systems that can process information faster and more efficiently will enable robots to complete more complex tasks, improve machine learning capabilities, and enhance autonomy. Whether it is for industrial automation, service robots, or anything in between, chiplet technology facilitates the creation of customized processing units tailored to specific applications, ensuring that robots can operate with greater precision, reliability, and adaptability in diverse environments.
Drones
The drone industry is poised for rapid advancement through the integration of chiplet technology, which will improve computational capabilities and efficiency significantly. For drones, which rely on sophisticated algorithms for navigation, image processing, and communication, chiplets offer a highly adaptable solution that can accommodate a range of functionalities. As chiplet technology enables more streamlined and powerful avionic systems, drone manufacturers can focus on their unique value-add such as enhancing flight stability, extending the range and introducing smart features that cater to commercial and recreational users.
Aerospace and Defense Systems
Aerospace and defense systems stand to benefit tremendously from adopting chiplet technology, which can deliver high-performance computing in a compact and energy-efficient form compared to many of the FPGA-based systems currently in use today. This technological advancement allows for more agile and responsive control systems, improved situational awareness, and robust data processing capabilities essential for modern defense applications. By leveraging chiplets, companies can design cutting-edge avionics that meet the stringent requirements of aerospace missions, ensuring superior performance across space exploration and military operations. Chiplets also solve the challenge of diverse technologies, enabling the mixing of die such as logic processing alongside RF and pure analog die. As a result, chiplet technology is set to become a cornerstone of innovation in the aerospace and defense sectors.
Offerings
Chiplet-Based Physical AI Platform and SoC Design Spanning IP, Chiplet Platforms, Systems, and Packaging
Integrating multiple heterogeneous on-package chiplets makes it easier to combine 2D and 2.5D dies from different sources, fabs, designs, and packaging technologies. This on-package mix and match of components for SoC construction is made possible by a variety of Cadence EDA and IP technologies. And with Cadence’s chiplet platform solutions and ecosystem, customers can realize their chiplet ambitions with increased cost efficiency and reduced time to market.
Chiplet-Based Physical AI Platform
Cadence offers a chiplet-based physical AI platform as an enabler of customer-designed systems, including chiplets as part of the Arm ecosystem. This platform includes a scalable architecture consisting of a base system chiplet that supports a flexible configuration, a configurable AI accelerator based on the Cadence Neo NPU, support for a CPU chiplet, and the incorporation of an optional domain-specific chiplet. Each utilizes the Cadence chiplet framework that encapsulates the subsystems into chiplets for cohesive communication between chiplets, including SoC-level control functionality for the security, safety, and control subsystems. Available unified reference software enables streamlined system bring-up and accelerates production software use-case development. Use of the Cadence Physical AI chiplet platform delivers significant time savings in project design cycles, thus significantly reducing engineering costs.
Cadence taped out its first Arm-based system chiplet, which integrates chiplet functionality, processors, system IP, and memory IP within a single package. It utilizes Cadence’s IP, EDA solutions, and Arm IP. Using Cadence’s chiplet framework, customers can maximize component reuse, minimize design efforts, support Arm CSA, and imec Automotive Chiplet Program, with UCIe standards-based connectivity, which will enable interoperability and connectivity with other chiplets.
Protocol IP for Chiplet Connectivity
Cadence offers a comprehensive portfolio of high-performance, silicon-proven Protocol IP tailored for chiplet-based designs. Supporting industry standards such as UCIe™, PCIe®, CXL™, and more, our IP enables seamless, low-latency, and power-efficient die-to-die communication. Whether you're building advanced multi-die systems or exploring next-generation heterogeneous integration, Cadence Protocol IP delivers the interoperability, scalability, and reliability needed to accelerate your chiplet innovation.
Reusable Verification IP
Users can enhance their verification process and boost productivity using reusable verification IP for chiplets. The Cadence Verification IP for UCIe is designed for easy integration into testbenches at the IP, chiplet, SoC, and system levels.
Multiphysics In-Design Analysis
Cadence multiphysics analysis solution plays a critical role in advancing chiplet technology by addressing heterogeneous integration complexities and system-level performance optimization. This solution provides a comprehensive platform for analyzing thermal, electromagnetic, and mechanical interactions within chiplets and their surrounding packaging. Predict and mitigate challenges such as thermal hotspots, signal and power integrity issues, and mechanical stress during the design phase. This proactive approach enables the creation of high-performance chiplets optimized for power efficiency, reliability, and seamless integration into advanced systems-in-package (SiPs). The solution also supports streamlined validation processes, ensuring accurate modeling of multi-chip interactions to reduce design risks and time-to-market.
Advanced IC Packaging
The implementation of chiplets into SiPs presents new challenges for system architects and designers. Cadence SiP design technology enables and integrates the exploration, capture, construction, optimization, and validation of complex multi-chip and discrete substrate assemblies. This streamlines the integration of multiple high-pin-count chips onto a single substrate, which is necessary for designing high-performance and complex packaging technologies.
Chiplet Assembly
The Cadence Integrity 3D-IC unified platform enables system planning and assembly of chiplets with a faster, more predictable path to multi-chiplet design closure. It provides a comprehensive solution for chiplet and multi-chiplet assembly that streamlines integration, implementation, and early analysis at the system level. By leveraging advanced capabilities such as a multi-technology database and seamless co-design within the Cadence Innovus Implementation System and Cadence Allegro X Advanced Package Designer, Integrity 3D-IC enables engineers to efficiently plan, implement, optimize, and analyze chip and package architectures.
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