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    • 数字设计与Signoff
      数字设计与 Signoff 概述

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

      全流程数字解决方案 相关产品 A-Z

      工具目录
      • 逻辑等效性检查
        • Products
        • Conformal Equivalence Checker
        • Conformal Smart LEC
      • SoC Implemenation and Floorplanning
        • Products
        • Innovus Implementation System
        • First Encounter Design Exploration and Prototyping
        • Virtuoso Digital Implementation
      • 形式验证与功能 ECO
        • Products
        • Conformal ECO Designer
      • 低功耗验证
        • Products
        • Conformal Low Power
      • RTL 综合
        • Products
        • Stratus High-Level Synthesis
        • Genus Synthesis Solution
        • Joules RTL Power Solution
        • Virtuoso Digital Implementation
      • 功耗分析
        • Products
        • Joules RTL Power Solution
      • SDC and CDC Signoff
        • Products
        • Conformal Litmus
        • Conformal Constraint Designer
      • 硅签收
        • Products
        • Pegasus Verification System
        • Quantus Extraction Solution
        • Tempus Timing Signoff Solution
        • Assura Physical Verification
        • Physical Verification System
        • CMP Predictor
        • MaskCompose Reticle and Wafer Synthesis
        • QuickView Signoff Data Analysis
        • LDE Electrical Analyzer
        • Process Proximity
        • Pattern Analysis
        • Litho Physical Analyzer
        • Voltus IC Power Integrity Solution
        • Voltus-Fi Custom Power Integrity Solution
      • Library Characterization
        • Products
        • Liberate Trio Characterization Suite
        • Liberate MX Memory Characterization
        • Liberate AMS Mixed-Signal Characterization
        • Liberate LV Library Validation Solution
        • Liberate Characterization Solution
        • Liberate Variety Statistical Characterization
      • 可测性设计
        • Products
        • Modus DFT Software Solution
      • 流程
        • 流程
        • 3D-IC
        • 先进工艺节点
        • 基于 ARM 的设计
        • Library Characterization Flow
        • 低功耗
        • 混合信号
    • 定制 IC/模拟/ RF 设计
      定制 IC /模拟/ RF 设计概述

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

      概述 相关产品 A-Z

      工具目录
      • 电路设计
        • Tools
        • What's New in Virtuoso
        • Virtuoso Schematic Editor
        • Virtuoso ADE Product Suite
      • 电路仿真
        • Tools
        • Spectre Simulation Platform
        • Spectre X Simulator
        • Spectre eXtensive Partitioning Simulator
        • Spectre RF Option
        • Spectre AMS Designer
      • 版图设计
        • Tools
        • What's New in Virtuoso
        • Virtuoso Layout Suite
      • 版图验证
        • Tools
        • Virtuoso DFM
        • Physical Verification System
        • Virtuoso Integrated Physical Verification System
      • 特征库提取
        • Tools
        • Liberate Trio Characterization Suite
        • Virtuoso Liberate MX Memory Characterization Solution
        • Virtuoso Liberate AMS Mixed-Signal Characterization Solution
        • Liberate Variety Statistical Characterization
        • Liberate Characterization Solution
        • Liberate LV Library Validation Solution
      • 流程
        • 流程
        • 电学感知设计(EAD)
        • 先进工艺节点
        • Virtuoso RF Solution
        • Virtuoso System Design Platform
        • 5G Systems and Subsystems
    • 系统设计与验证
      系统设计与验证概述

      Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.

      系统验证套件 相关产品 A-Z

      工具目录
      • 调试纠错分析
        • Tools
        • Indago Debug Platform
        • Indago Debug Analyzer App
        • Indago Embedded Software Debug App
        • Indago Protocol Debug App
        • SimVision Debug
      • 硬件仿真加速器
        • Tools
        • Palladium Z1 Enterprise Emulation System
        • Palladium XP Series
        • Palladium Dynamic Power Analysis
        • Palladium Hybrid
        • SpeedBridge Adapters
        • Emulation Development Kit
        • Virtual JTAG Debug Interface
        • Accelerated VIP
        • QuickCycles Services
        • VirtualBridge Adapters
      • 形式化验证与静态验证
        • Tools
        • JasperGold Formal Verification Platform (Apps)
        • Assertion-Based Verification IP
      • FPGA 原型验证
        • Tools
        • Protium S1 Desktop Prototyping Platform
        • Protium X1 Enterprise Prototyping Platform
        • SpeedBridge Adapters
      • 验证规划与管理
        • Tools
        • vManager Metric-Driven Signoff Platform
      • 仿真与 Testbench 验证
        • Tools
        • Xcelium Parallel Simulator
        • Incisive Enterprise Simulator
        • Incisive Functional Safety Simulator
        • Incisive Specman Elite
      • 软件驱动验证
        • Tools
        • Perspec System Verifier
        • Indago Embedded Software Debug App
        • Virtual System Platform
      • 验证IP(VIP)
        • Tools
        • Accelerated Verification IP
        • Assertion-Based VIP
        • Verification IP (VIP) Catalog
      • 流程
        • 流程
        • 基于 ARM 设计的验证方案
        • 汽车功能安全性验证
        • 基于覆盖率度量的验证签收
        • 混合信号验证
        • 低功耗验证方法学
    • IP
      Cadence IP 主页

      这是一个开放的 IP 平台帮助您的APP驱动的 SoC 实现客户化设计

      了解更多

      工具目录
      • Interface IP
        • IP
        • PCI Express IP
        • CCIX IP
        • USB IP
        • SerDes IP
        • Ethernet IP
        • MIPI IP
        • HD Display IP
      • Denali Memory IP
        • IP
        • NAND Flash IP
        • DDR IP
        • HBM2 IP
        • SD / SDIO / eMMC IP
        • Octal and Quad SPI Flash Controller and PHY IP
      • Tensilica 处理器 IP
        • IP
        • HiFi DSPs for Audio, Voice, and Speech
        • ConnX DSPs for Radar, Lidar, and Communications
        • Vision DSPs for Imaging, Vision, and AI
        • Fusion DSPs for IoT
        • DNA Processor Family for On-Device AI
        • Tensilica Customizable Processors
        • Tensilica Reference Configuration
      • Analog IP
        • IP
        • Analog IP
      • System / Peripherals IP
        • IP
        • 8051 Microprocessor IP
        • System Bus Peripherals
        • Audio Controllers
      • 验证 IP
        • IP
        • Accelerated VIP
        • Assertion-Based VIP
        • Memory Models
        • Simulation VIP
        • Productivity Tools
        • Interconnect Solution
    • IC 封装设计与分析
      IC 封装设计与分析概述

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

      概述 相关产品 A-Z

      工具目录
      • IC 封装设计
        • Products
        • Allegro Package Designer
        • SiP Digital Architect
      • SI/PI 协同分析方案
        • Products
        • Allegro Sigrity SI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity Package Assessment and Extraction Option
        • Allegro Sigrity PI Base
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI 分析点工具
        • Products
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity Speed2000
        • Sigrity SystemSI
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity XtractIM
        • Sigrity XcitePI Extraction
      • 跨平台协同设计与分析
        • Products
        • OrbitIO Interconnect Designer
        • IO-SSO Analysis Suite
      • 流程
        • 流程
        • Cross-Substrate互连
        • IC/封装/PCB协同设计
        • InFO封装技术
        • Sigrity最新技术
        • Virtuoso System Design Platform
        • PDN设计
    • SYSTEM INNOVATION
    • 系统分析
      系统分析概述

      Cadence®系统分析解决方案提供高精度的电磁提取和仿真分析,确保您的系统在不同条件下正常运行。

      概述 相关产品 A-Z

      工具目录
      • Electromagnetic Solutions
        • Tools
        • Clarity 3D全波求解器
        • Sigrity XcitePI Extraction
        • Sigrity XtractIM
        • Sigrity PowerSI
      • Thermal Solutions
        • Tools
        • Celsius Thermal Solver
      • Flows
    • 嵌入式原型验证
    • PCB 设计与分析
      PCB 设计与分析概述

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

      概述 相关产品 A-Z 生态服务搜索

      工具目录
      • 原理图设计
        • Tools
        • Allegro Design Entry Capture/Capture CIS
        • Allegro Design Publisher
        • Allegro Design Authoring
        • Allegro FPGA System Planner
      • PCB 版图设计
        • Tools
        • Allegro PCB Designer
        • OrCAD PCB Designer
      • 库与设计数据管理
        • Tools
        • Allegro ECAD-MCAD Library Creator
        • Allegro EDM Solution
        • Allegro PCB Librarian
        • Allegro Pulse
      • 模拟/混合信号仿真
        • Tools
        • Allegro PSpice Simulator
        • OrCAD PSpice Designer
      • SI/PI 协同分析方案
        • Tools
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity SI Base
        • Allegro Sigrity PI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI 分析点工具
        • Tools
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity SystemSI
        • Sigrity Speed2000
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity PowerSI 3D EM Extraction Option
      • Allegro最新技术
        • Tools
        • Board Layout
        • Schematic Capture
        • Data Management
      • Sigrity最新技术
        • Tools
        • Sigrity 2018 Release
        • Sigrity Tech Tips
      • 流程
        • 流程
        • Multi-Board PCB System Design
        • 产品创建
        • ECAD MCAD 协同设计
        • Allegro Right First-Time Design
        • IO-SSO分析套件
        • 3D System Design Solutions
        • PDN设计
        • LPDDR4 完整分析方案
        • 功耗感知信号完整性分析
        • 接口感知方法
        • Sigrity串行链路分析
    • PERVASIVE INTELLIGENCE
    • Tensilica 处理器 IP
    • 机器学习
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    • INDUSTRIES
    • 5G Systems and Subsystems
    • 航天与国防
    • 汽车电子解决方案
    • TECHNOLOGIES
    • 3D-IC 设计
    • 先进工艺节点
    • Arm 解决方案
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    • 低功耗
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    • 光学
  • 技术服务
    • 技术服务概要

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    • 设计服务
    • 培训
    • 设计方法学服务
    • 虚拟集成化计算机辅助设计 (VCAD)
  • 支持与培训
    • 技术支持
      支持概要

      24小时全球范围的技术支持。

      了解更多 登录技术支持

      • 支持流程
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          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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        • 24/7 Support - Cadence Online Support

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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      • 客户支持联系人
        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

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        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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    • 全球培训课程目录
    • Custom IC / Analog / RF Design
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Circuit Design and Simulation
        • Featured Courses
        • Virtuoso ADE Assembler Series
        • Virtuoso ADE Verifier
        • Virtuoso Schematic Editor
        • Mixed Signal Simulations Using AMS Designer
        • Spectre Accelerated Parallel Simulator
        • Additional Courses
      • Electrically-Aware Design
        • Featured Courses
        • Physical Verification System
        • Virtuoso Analog Design Environment
        • Virtuoso Electrically-Aware Design with Layout-Dependent Effects
        • Virtuoso Schematic Editor
        • Quantus QRC Extraction Series
        • Spectre Accelerated Parallel Simulator
      • Infrastructure
        • Featured Courses
        • SKILL Development of Parameterized Cells
        • SKILL Language Programming
        • SKILL Language Programming Introduction
        • SKILL Programming for IC Layout Design
      • Layout Design and Verification
        • Featured Courses
        • Virtuoso Layout Pro Series
        • Virtuoso Space-Based Router
        • Virtuoso Floorplanner
        • Quantus QRC Extraction Series
        • Using Virtuoso Constraints Effectively
        • Virtuoso Connectivity-Driven Layout Transition
        • Physical Verification System
      • Library Characterization
        • Featured Courses
        • Cadence Library Characterization and Validation
        • Spectre Accelerated Parallel Simulator
        • Virtuoso ADE Assembler Series
      • Modeling
        • Featured Courses
        • Analog Modeling with Verilog-A
        • Behavioral Modeling with VHDL-AMS
        • Behavioral Modeling with Verilog-AMS
        • Mixed Signal Simulations Using AMS Designer
        • Real Modeling with SystemVerilog
        • Real Modeling with Verilog-AMS
        • Mixed-Signal IP and Testbench Reuse
      • RF Design
        • Featured Courses
        • Quantus QRC Transistor-Level T1: Overview and Technology Setup
        • Quantus QRC Transistor-Level T2: Parasitic Extraction
        • Quantus QRC Transistor-Level T3: Extracted View Flows and Advanced Features
        • Spectre Accelerated Parallel Simulator
      • Variation Aware Design
        • Featured Courses
        • Virtuoso ADE Assembler S1: Introducing the Assembler Environment
        • Virtuoso ADE Assembler S3: Circuit Checks, Device Asserts, and Reliability Analysis
        • Variation Analysis Using the Virtuoso ADE Assembler
        • Virtuoso Spectre Pro Series
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • Languages and Methodologies
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Assertions
        • Featured Courses
        • Verification with PSL
      • Behavioral Language for AMS Simulation
        • Featured Courses
        • Behavioral Modeling with VHDL-AMS
        • Behavioral Modeling with Verilog-AMS
        • Real Modeling with SystemVerilog
        • Real Modeling with Verilog-AMS
      • Scripting
        • Featured Courses
        • Perl for EDA Engineering
        • Tcl Scripting for EDA
      • Specman and UVMe
        • Featured Courses
        • Specman Advanced Training
        • Specman Fundamentals for Block-Level Environment Developers
      • SystemC
        • Featured Courses
        • C++ Language Fundamentals for Design and Verification
        • SystemC Language Fundamentals
        • SystemC Transaction-Level Modeling (TLM 2.0)
      • SystemVerilog and UVM
        • Featured Courses
        • Real Modeling with SystemVerilog
        • SystemVerilog Advanced Register Verification Using UVM
        • SystemVerilog for Design and Verification
        • SystemVerilog for Verification
      • Verilog and VHDL
        • Featured Courses
        • VHDL Language and Application
        • Verification with PSL
        • Verilog for VHDL Users
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Digital Design and Signoff
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Block and Hierarchical Implementation
        • Featured Courses
        • Analog-on-Top Mixed-Signal Implementation
        • Innovus Implementation System (Block)
        • Innovus Implementation System (Hierarchical)
      • Equivalence Checking
        • Featured Courses
        • Encounter Conformal ECO
        • Logic Equivalence Checking with Conformal EC
      • Silicon Signoff
        • Featured Courses
        • Voltus Power-Grid Analysis and Signoff
      • Synthesis
        • Featured Courses
        • Advanced Synthesis with Genus Stylus Common UI
        • Genus Synthesis Solution with Stylus Common UI
        • Low-Power Synthesis Flow with Genus Stylus CommonUI
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • IC Package Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Cross-Platform Co-Design and Analysis
        • Featured Courses
        • OrbitIO System Planner
        • SiP Layout
      • IC Package Design
        • Featured Courses
        • SiP Layout
      • SI/PI Analysis Integrated Solution
        • Featured Courses
        • Allegro Sigrity PI
        • Allegro Sigrity Package Assessment and Model Extraction
        • Allegro Sigrity SI Foundations
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • SI/PI Analysis Point Tools
        • Featured Courses
        • Allegro Sigrity Package Assessment and Model Extraction
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • PCB Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Analog/Mixed-Signal Simulation
        • Featured Courses
        • Allegro AMS Simulator Advanced Analysis
        • Analog Simulation with PSpice
      • Design Authoring
        • Featured Courses
        • Allegro Design Entry HDL Basics
        • Allegro Design Entry HDL SKILL Programming Language
        • Allegro Design Entry Using OrCAD Capture
        • Allegro System Architect
        • Allegro Team Design Authoring
      • Library and Design Data Management
        • Featured Courses
        • Allegro Design Workbench for Administrators
        • Allegro Design Workbench for Engineers and Designers
        • Allegro Design Workbench for Librarians
        • Allegro PCB Librarian
      • PCB Layout
        • Featured Courses
        • Allegro High-Speed Constraint Management
        • Allegro PCB Editor Basic Techniques
        • Allegro PCB Editor Intermediate Techniques
        • Allegro PCB Router Basics
      • SI/PI Analysis Integrated Solution
        • Featured Courses
        • Allegro Sigrity PI
        • Allegro Sigrity SI Foundations
        • Sigrity PowerSI for Model Generation and Analysis
        • Sigrity PowerDC and OptimizePI
      • SI/PI Analysis Point Tools
        • Featured Courses
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • System Design and Verification
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Emulation and Acceleration
        • Featured Courses
        • Protium Rapid Prototyping Platform
      • Formal Verification
        • Featured Courses
        • JasperGold Formal Fundamentals
        • Verification with PSL
      • Planning and Management
        • Featured Courses
        • Foundations of Metric Driven Verification
        • Metric Driven Verification using Incisive vManager
      • Scripting
        • Featured Courses
        • Perl for EDA Engineering
        • Tcl Scripting for EDA
      • Simulation, Testbench and Debug
        • Featured Courses
        • Xcelium Fault Simulator
        • Incisive Functional Safety Simulator
        • Low-Power Simulation with IEEE Std 1801 UPF
      • Specman and UVMe
        • Featured Courses
        • Specman Advanced Training
        • Specman Fundamentals for Block-Level Environment Developers
      • SystemC
        • Featured Courses
        • C++ Language Fundamentals for Design and Verification
        • SystemC Language Fundamentals
        • SystemC Transaction-Level Modeling (TLM 2.0)
      • SystemVerilog and UVM
        • Featured Courses
        • Real Modeling with SystemVerilog
        • SystemVerilog Advanced Register Verification Using UVM
        • SystemVerilog for Design and Verification
        • SystemVerilog for Verification
      • Verilog and VHDL
        • Featured Courses
        • VHDL Language and Application
        • Verification with PSL
        • Verilog for VHDL Users
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Tensilica Processor IP
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • ConnX DSPs
        • Featured Courses
        • Tensilica ConnX BBE16EP Baseband Engine
        • Tensilica ConnX BBE32EP Baseband Engine
        • Tensilica ConnX BBE64EP Baseband Engine
      • Fusion DSPs
        • Featured Courses
        • Tensilica Fusion F1 DSP
        • Tensilica Fusion G3 DSP
      • HiFi DSPs
        • Featured Courses
        • Tensilica HiFi 2/EP/Mini Audio Engine ISA
        • Tensilica HiFi 3 Audio Engine ISA
        • Tensilica Audio Codec API
      • Tensilica Processors
        • Featured Courses
        • Tensilica Processor Fundamentals
        • Tensilica Instruction Extension Language and Design
        • Tensilica Xtensa Hardware Verification and EDA
        • Tensilica Xtensa Processor Interfaces
      • Vision DSPs
        • Featured Courses
        • Tensilica Vision P5 DSP
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

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Digital Advanced Node

Best quality of results for challenging FinFET designs

 

  • Advanced-Node Solutions
  • Custom/Analog Advanced Node
  • Digital Advanced Node

Key Benefits

  • Massively parallel technology facilitates the handling of the large data size and complexity of advanced nodes
  • Smart algorithms implemented over integrated engines provide best PPA benefits
  • Comprehensive full-flow integrated digital toolset for design creation, implementation, and signoff enabling faster convergence and design closure for advanced nodes
Meeting the challenge of advanced nodes

Advanced FinFET devices and planar devices with FD-SOI technology improve power, performance, and area (PPA), but create additional design challenges. Cadence developed its revolutionary full-flow digital toolset to address these design challenges at the design creation, implementation, and signoff stages. Here are just some of the issues designers can run into with these transistors:

  • Leakage power is reduced, but now dynamic power becomes more significant
  • Double patterning is used to enhance feature density as single-pass lithography falls short
  • Placement and optimization must consider new advanced-node base-layer constraints
  • Larger port capacitance of devices adds to total capacitance on wires
  • Designs operate at lower voltages, so design flows need to handle lower vdds
  • Electromigration and IR become a bigger concern with increased drive strength and high-resistance wires
  • On-chip variation plays a bigger role and must be mitigated through correct statistical algorithms
  • Transistor self-heating effects can affect signal RMS current

The Cadence® Full-Flow Digital Implementation and Signoff tools can handle and support all the special requirements of today’s FinFET and advanced-node FD-SOI designs. These tools prevent and correct harmful lithography hotspots, random defects, on-chip variation, and variation due to chemical-mechanical polishing. Using rule- and model-based in-design analysis (pre-qualified and closely related with foundry process simulation), the Cadence Innovus™ Implementation System minimizes risk upfront and prevents unexpected design re-spins and late-stage iterations.

Designing for double patterning and beyond

As design is moving below 20nm, fabs are employing double patterning to enhance the feature density, as single lithographic exposure generally is not enough to provide sufficient resolution. At 16nm and 14nm, shapes are so close that single-pass lithography has many interference effects, and multi-pass lithography is required. With two-pass lithography, each pass prints one mask of double-pitch wires. When both passes are complete, a single layout with minimum spacing wires is created.

At 7nm, explicit full-flow coloring is required during design. RC characteristics are color dependent, even on the same metal layer. Older software for IC design can’t handle the double patterning or explicit coloring required. But Cadence’s implementation and signoff tools were designed, from the start, to help designers deal with these and other effects of very small geometries.

Digital toolset optimized for advanced nodes

Cadence completely re-invented its digital tool set for advanced nodes, starting with a unified software architecture. This integrated digital architecture is based on a foundation of core common engines and full-flow optimizations. When new features are added in one place, multiple applications benefit. This enables smarter software, with fewer bugs, rapid feature deployment for newer nodes, accurate early prediction, and convergent correlation.

Unified Software Architecture

 

The Cadence full-flow digital solution offers massive parallelization that works to your advantage. Other point-tool-oriented flows create inefficiencies due to parallelism, with multiple bottlenecks between synthesis and implementation and between optimization and signoff. By using full-flow parallelism, Cadence avoids those bottlenecks and provides a much faster turnaround time.

Full Flow Parallelism

 

Design creation starts with the Cadence Genus™ Synthesis Solution, which utilizes an early physical approach for placement, congestion predictability, layer assignment, layer-aware buffering, RTL optimization, and considerations for area, timing, and power. With a unified placement engine, global routing engine, delay calculation, and parasitic extraction, the Genus solution prepares your design for implementation.

The Cadence Innovus Implementation System provides full support for coloring, double patterning and a unique via pillar methodology for high-performance computing requirements. The GigaPlace™ Engine, which uses a look-ahead placement approach, includes features that are useful for advanced-node designs, including activity-driven placement, slack- and power-driven placement, pin-access-aware placement, and IR-driven placement. The NanoRoute™ Advanced Digital Router is optimized for highly complex designs that include multiple CPUs and other complex logic. The GigaOpt™ Optimizer considers advanced-node characteristics such as correct layer selection for optimal buffering. Layer-aware route-driven optimization technology provides huge improvements in timing closure.

Signoff speed and efficiency

Over the past few years, Cadence has introduced totally revamped tools to facilitate advanced-node signoff. These tools are all integrated, and include our Quantus™ Extraction Solution; the Liberate™ Characterization portfolio providing robust solutions for the characterization, variation modeling, and validation of foundation IP, from standard cells, I/Os, and complex multi-bit cells to memories and mixed-signal blocks; the Tempus™ Timing Signoff Solution for signoff static timing analysis; the Voltus™ IC Power Integrity Solution; and the Pegasus™ Verification System for massively parallel physical signoff and DRC, LVS, and DFM.

These sophisticated signoff tools are fully integrated with the Cadence synthesis and implementation tool sets to provide designers with one integrated tool flow for the entire design process.

In summary, Cadence’s Advanced-Node Digital Implementation Solution with massive parallelization, shared engines infrastructure, and in-design signoff offers a unique and comprehensive solution for designing breakthrough technology using FinFETs or FD-SOI technology at advanced nodes.

Reality Is Not Linear

The changing landscape
of physical design

HEAR THE INTERVIEW

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Silicon Signoff and Verification - 16nm FinFET Challenges and Features

Offering Leading Edge Total Solutions - GLOBALFOUNDRIES Design Ready 14nm Eco System

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