Key Benefits

Increase
Silicon Quality

Multi-CPU enabled, advanced, and integrated DPT-aware engines for digital and custom implementation, analysis, and verification

Boost
Productivity

Prevent verification and DFM issues upfront with automated handling of large, low-power, mixed-signal designs

Speed Ramp
to Volume

Reduce iterations within the flow and limit silicon re-spins

Manage
Yield

Optimize interconnect with variation-aware in-design signoff and integrated DFM flows

Offerings

Leverage a complete, consistent, and converging flow across Innovus™ digital and Virtuoso® custom implementation technologies to address design-for-manufacturing (DFM) and variability effects earlier.

By integrating color-aware DPT flows with model-based DFM, IR drop analysis, timing and power analysis, and verification in a comprehensive prevent-validate-finalize flow, the Cadence® solution can tackle huge designs and provides significant productivity gains over traditional design closure methodologies.

Overview

Advanced-node processes challenge custom/analog designers with the complex interdependency of manufacturing and variability, on top of increasing power and performance specifications. The Cadence® Virtuoso advanced-node platform has an innovative set of capabilities that enable designers to take full advantage of the silicon at these process nodes.

The Virtuoso advanced-node platform improves individual point tools to handle these challenges, as well as enables new design methodologies that allow for rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers—essential to designing efficiently at advanced-process nodes.

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Overview

Advanced FinFET devices and planar devices with FD-SOI technology improve power, performance, and area (PPA), but create additional design challenges. Cadence developed its revolutionary full-flow digital toolset to address these design challenges at the design creation, implementation, and signoff stages.

The Cadence® Full-Flow Digital Implementation and Signoff tools can handle and support all the special requirements of today’s FinFET and advanced-node FD-SOI designs. These tools prevent and correct harmful lithography hotspots, random defects, on-chip variation, and variation due to chemical-mechanical polishing. Using rule- and model-based in-design analysis (pre-qualified and closely related with foundry process simulation), the Cadence Innovus™ Implementation System minimizes risk upfront and prevents unexpected design re-spins and late-stage iterations.

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