Key Benefits
- Increases quality of silicon: Multi-CPU enabled, advanced, and integrated DPT-aware engines for digital and custom implementation, analysis, and verification
- Boosts productivity: Automated handling of large, low-power, mixed-signal designs with context-aware placement and routing, in-design signoff, and verification prevents the majority of verification and DFM issues upfront
- Speeds ramp to volume: Reduces iterations within the flow and limits silicon re-spins
- Manages yield: Variation-aware in-design signoff and integrated DFM flows allow you to optimize interconnect
Complete, integrated, and silicon-proven 10nm and below design flows for custom/analog, digital, and mixed-signal system-on-chip (SoC) designs.
Escalating data volume and denser, more complex chips are testing the limit of traditional routing architectures. Engineers face a predictability crisis riddled with silicon failures, performance degradation, and prolonged design schedules. And new process and design innovations—high-k metal gate, SOI, 3D-IC packaging—are intensifying the pressures of adoption and rapid deployment. To manage lower power and higher performance goals in smaller form factors, engineers need a design environment and methodology that considers all advanced node design and manufacturing requirements simultaneously.
The Cadence® Advanced Node Solution provides a complete, consistent, and converging flow across Innovus™ digital and Virtuoso® custom implementation technologies to address design-for-manufacturing (DFM) and variability effects (lithography, CMP, thermal, process variations) in the early stages of the design flow. By integrating color-aware DPT flows with model-based DFM, IR drop analysis, timing and power analysis, and verification in a comprehensive prevent-validate-finalize flow, the Cadence solution can tackle huge designs and provides significant productivity gains over traditional design closure methodologies.
