Multi-CPU enabled, advanced, and integrated DPT-aware engines for digital and custom implementation, analysis, and verification
Prevent verification and DFM issues upfront with automated handling of large, low-power, mixed-signal designs
Reduce iterations within the flow and limit silicon re-spins
Optimize interconnect with variation-aware in-design signoff and integrated DFM flows
Leverage a complete, consistent, and converging flow across Innovus™ digital and Virtuoso® custom implementation technologies to address design-for-manufacturing (DFM) and variability effects earlier.
By integrating color-aware DPT flows with model-based DFM, IR drop analysis, timing and power analysis, and verification in a comprehensive prevent-validate-finalize flow, the Cadence® solution can tackle huge designs and provides significant productivity gains over traditional design closure methodologies.
Advanced-node processes challenge custom/analog designers with the complex interdependency of manufacturing and variability, on top of increasing power and performance specifications. The Cadence® Virtuoso advanced-node platform has an innovative set of capabilities that enable designers to take full advantage of the silicon at these process nodes.
The Virtuoso advanced-node platform improves individual point tools to handle these challenges, as well as enables new design methodologies that allow for rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers—essential to designing efficiently at advanced-process nodes.Learn More
Advanced FinFET devices and planar devices with FD-SOI technology improve power, performance, and area (PPA), but create additional design challenges. Cadence developed its revolutionary full-flow digital toolset to address these design challenges at the design creation, implementation, and signoff stages.
The Cadence® Full-Flow Digital Implementation and Signoff tools can handle and support all the special requirements of today’s FinFET and advanced-node FD-SOI designs. These tools prevent and correct harmful lithography hotspots, random defects, on-chip variation, and variation due to chemical-mechanical polishing. Using rule- and model-based in-design analysis (pre-qualified and closely related with foundry process simulation), the Cadence Innovus™ Implementation System minimizes risk upfront and prevents unexpected design re-spins and late-stage iterations.Learn More
Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications
Cadence Unveils Expanded Virtuoso Advanced-Node Platform for 7nm Processes
Toshiba Electronic Device Solutions Overcomes Complexities of Advanced-Node Designs
Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies