- Digital Design and Signoff (178)
- Innovus Implementation System (78)
- Tempus Timing Signoff Solution (64)
- Silicon Signoff (62)
- Quantus QRC Extraction (53)
- Voltus IC Power Integrity Solution (45)
- Block Implementation (41)
- Genus Synthesis Solution (40)
- Synthesis (35)
- Modus Test Solution (30)
- 测试 (22)
- Voltus-Fi Custom Power Integrity Solution (22)
- Physical Verification System (22)
- Hierarchical Design and Floor Planning (18)
- Conformal Low Power (14)
- Innovus Implementation Solution (14)
- Custom IC - Analog - RF Design (14)
- Virtuoso Layout Suite (14)
- System Design and Verification (13)
- Stratus High-Level Synthesis (11)
- Spectre Accelerated Parallel Simulator (10)
- Pegasus Verification System (9)
- Liberate Trio Characterization Suite (9)
- Joules RTL Power Solution (9)
- Spectre Circuit Simulator (9)
- Flows (9)
- Equivalence Checker (9)
- Virtuoso ADE Product Suite (9)
- CMP Predictor (9)
- LDE Electrical Analyzer (9)
- Virtuoso Schematic Editor (9)
- Virtuoso Liberate (8)
- Spectre eXtensive Partitioning Simulator (XPS) (8)
- Litho Physical Analyzer (8)
- Conformal Overview (7)
- Conformal ECO Designer (7)
- Characterization (6)
- Virtuoso Liberate MX (6)
- Virtuoso Liberate AMS (6)
- Low Power Validation (6)
- Functional ECO (6)
- Circuit Simulation (6)
- Library Validation (5)
- Virtuoso Layout Suite for Electrically Aware Design (5)
- Virtuoso Variety (5)
- Process Variation Modeling (5)
- Virtuoso ADE Assembler (5)
- Virtuoso ADE Verifier (5)
- Virtuoso Liberate LV (5)
- Quickview Signoff Data Analysis Environment (5)
- Virtuoso Analog Design Environment (5)
- Layout Verification (5)
- Virtuoso ADE Explorer (5)
- OrbitIO Interconnect Designer (5)
- Sigrity PowerDC (5)
- MaskCompose Reticle and Wafer Synthesis Suite (5)
- SDC and CDC Signoff (4)
- Conformal Equivalence Checker (4)
- IC Package Design and Analysis (4)
- Pattern Analysis (4)
- SiP Layout (4)
- SiP Layout WLCSP (4)
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The Cadence® Quantus™ Extraction Solution is a next-generation parasitic extraction tool for digital and custom/analog flows, providing the fastest performance and scalability and best-in-class accuracy us...
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Interactive Short Locator: Establishing Efficiency and Predictability in the LVS Short Debug Process for Advanced SoC Designs Technical Paper
Interactive Short Locator technology in the Cadence Physical Verification System provides an efficient debug solution that employs a dedicated analysis engine and interactive workflow to locate shorts quic...
Genus Synthesis Solution is a next-generation RTL synthesis and physical synthesis tool that delivers an up to 10X boost in RTL design productivity with up to 5X faster turnaround times.
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Pushing the Performance Boundaries of ARM Cortex-M Processors for Future Embedded Design White Paper
This paper examines the challenges of design automation methodologies in the new ARM Cortex-M processor: how to get maximum performance while designing for a set power budget and how to get maximum power s...