Filter Results:
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26 Result(s) Found
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A Better Tool for Functional Verification of Low-Power Designs with IEEE 1801 UPF White PaperTo examine simulation and emulation technologies for a thorough, yet faster functional verification of low-power systems on chip (SoCs), this paper first reviews the fundamental sources and reduction techn...
657 KB
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Texas Instruments and Cadence Verification Success StoryBy combining Palladium XP DPA with Encounter Power System TI achieved close correlation between the architects power estimation and actual silicon power consumption measurements enabling the company to del...
468 KB
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Building Energy-Efficient ICs from the Ground Up White PaperThe design, implementation, and verification tools and flows provided by Cadence address all areas of power management and solve the SoC low-power problem.
344 KB
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UVM methodology based Verification Environment for Imaging IPs/SoCsAbhishek Jain, Technical Manager at STMicroelectronics, talks about working with the Cadence Incisive Verification Solution to deploy a UVM multi-language, low-power verification methodology resulting in e...
23 Jun 2016
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MediaTek Gets High-Quality Smart Devices to Market Quickly with Palladium PlatformIn this video, Andrew Chang, MediaTek corporate vice president, talks about the challenges in creating today's smart devices complexity, push for higher performance, and the need for lower power. Learn ho...
22 Aug 2015
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Developing 4G Wireless Designs with Cadence CPF-Driven Low-Power SolutionAntoine Dejonghe, Green Radio Program Manager at imec, highlights the use of the Cadence CPF-Driven Advanced Low-Power Solution that accelerates the company's next generation 4G wireless designs.
15 Jun 2016
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5 Steps to Your First Power Shut-off (PSO) VerificationAdam Sherer and Mickey Rodriguez from Cadence discuss 5 Steps to Your First Power Shut-off (PSO) Verification. Low-Power Verification Raises Silicon Quality and complex conditions open risk for bug escapes...
22 Aug 2015
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6 Must Know Tips to Optimize LPDDR and Wide I/O PerformanceHear Wendy Eisasser discusses 6 Must Know Tips to optimize LPDDR and Wide I/O performance. LPDDR and Wide I/O Compete for Mobile Sockets and which option is best for your next design. A comparison of Memor...
22 Aug 2015
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System Level Low Power Verification Using Palladium and CPFPete Hardee from Cadence discusses System Level Low Power Verification Using Palladium and CPF. An overview of Low Power verification, verifying power management under software control, power analysis wit...
22 Aug 2015
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Freeescale Semiconductor - Cadence Low-Power Solution for Kinetis SoCAnis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC
28 May 2016
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